Nonvolatile semiconductor memory device

• US 10,460,812 B2
• Filed: 01/29/2019
• Issued: 10/29/2019
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Maeda, Takashi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/260,247
• Publication Number:
  US 20190156898A1
• Time in Patent Office: 273 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claims

1. A memory device, comprising:

a memory cell array including a first memory block,

the first memory block including a first sub block and a second sub block,

the first sub block including a first memory unit and a second memory unit,

the first memory unit including a first drain side selective transistor, a plurality of first memory cells, a first source side selective transistor, a plurality of second memory cells, and a first connecting portion that connects the first memory cells and the second memory cells in series,

the second memory unit including a second drain side selective transistor, a plurality of third memory cells, a second source side selective transistor, a plurality of forth memory cells and a second connecting portion that connects the third memory cells and the fourth memory cells in series;

the second sub block including a third memory unit and a fourth memory unit,

the third memory unit including a third drain side selective transistor, a plurality of fifth memory cells, a third source side selective transistor, a plurality of sixth memory cells and a third connecting portion that connects the fifth memory cells and the sixth memory cells in series;

the fourth memory unit including a fourth drain side selective transistor, a plurality of seventh memory cells, a fourth source side selective transistor, a plurality of eighth memory cells and a fourth connecting portion that connects the seventh memory cells and the eighth memory cells in series;

a first bit line connected to the first drain side selective transistor and the third drain side selective transistor;

a second bit line connected to the second drain side selective transistor and the fourth drain side selective transistor;

a plurality first word lines connected to gates of the first memory cells, gates of the third memory cells, gates of the fifth memory cells, and gates of the seventh memory cells, respectively,

a plurality second word lines connected to gates of the second memory cells, gates of the fourth memory cells, gates of the sixth memory cells, and gates of the eighth memory cells respectively;

a first source side select gate line connected to a gate of the first source side selective transistor and a gate of the second source side selective transistor;

a second source side select gate line connected to a gate of the third source side selective transistor and a gate of the fourth source side selective transistor; and

a control circuit which applies a first voltage to the first bit line and the second bit line, a second voltage which is lower than the first voltage to the first source side select gate line, a third voltage which is higher than the second voltage to the second source side select gate line, a fourth voltage which is lower than the second voltage to the plurality of first word lines and the plurality of second word lines, while erase operation to the first sub block is operated.

2. The memory device according to claim 1, wherein the first source side select gate line and the second source side select gate line are electrically disconnected from each other and capable to apply a voltage independently.

3. The memory device according to claim 1, wherein one of the first word lines and a corresponding one of the second word lines are disposed in the same layer, respectively, and the one of the first word lines and the corresponding one of the second word lines are electrically disconnected from each other.

4. The memory device according to claim 1, wherein the first connecting portion, the second connecting portion, the third connecting portion, and the fourth connecting portion include poly silicon.