Nonvolatile memory devices providing reduced data line load
First Claim
1. A nonvolatile memory device comprising:
- a memory cell array;
a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising;
a first high-voltage circuit comprising a first bit line selection circuit connected to the first plurality of bit lines;
a first bit line shut-off circuit connected to the first plurality of bit lines via the first bit line selection circuit; and
a first latch circuit configured to input and output data via a first data line; and
a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising;
a second high-voltage circuit comprising a second bit line selection circuit connected to the second plurality of bit lines;
a second bit line shut-off circuit connected to the second plurality of bit lines via the second bit line selection circuit; and
a second latch circuit configured to input and output data via a second data line,wherein the first bit line selection circuit and the second bit line selection circuit are on a first region of a main surface of a substrate, the first bit line shut-off circuit and the second bit line shut-off circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate,wherein the first region, the second region, and the third region are sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, andwherein a width of the first data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines.
1 Assignment
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Accused Products
Abstract
A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.
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Citations
20 Claims
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1. A nonvolatile memory device comprising:
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a memory cell array; a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising; a first high-voltage circuit comprising a first bit line selection circuit connected to the first plurality of bit lines; a first bit line shut-off circuit connected to the first plurality of bit lines via the first bit line selection circuit; and a first latch circuit configured to input and output data via a first data line; and a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising; a second high-voltage circuit comprising a second bit line selection circuit connected to the second plurality of bit lines; a second bit line shut-off circuit connected to the second plurality of bit lines via the second bit line selection circuit; and a second latch circuit configured to input and output data via a second data line, wherein the first bit line selection circuit and the second bit line selection circuit are on a first region of a main surface of a substrate, the first bit line shut-off circuit and the second bit line shut-off circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate, wherein the first region, the second region, and the third region are sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, and wherein a width of the first data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A nonvolatile memory device comprising:
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a memory cell array; a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising a first high-voltage circuit connected to the first plurality of bit lines, a first low-voltage circuit connected to the first plurality of bit lines via the first high-voltage circuit, and a first latch circuit configured to input and output data via a first data line; and a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising a second high-voltage circuit connected to the second plurality of bit lines, a second low-voltage circuit connected to the second plurality of bit lines via the second high-voltage circuit, and a second latch circuit configured to input and output data via a second data line, wherein the first high-voltage circuit and the second high-voltage circuit are on a first region of a main surface of a substrate, the first low-voltage circuit and the second low-voltage circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate, wherein the first region, the second region, and the third region are sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, and wherein the first high-voltage circuit and the second high-voltage circuit are configured to receive respective voltages comprising higher ranges than voltages that the first low-voltage circuit and the second low-voltage circuit are configured to receive. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A nonvolatile memory device comprising:
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a memory cell array; and a page buffer circuit including a plurality of high-voltage circuits, a plurality of low-voltage circuits, and a plurality of latch circuits on a substrate, wherein the substrate includes a high-voltage region in which the high-voltage circuits are arranged, a low-voltage region in which the low-voltage circuits are arranged, and latch region in which the latch circuits are arranged, wherein the high-voltage region, the low-voltage region, and the latch region are sequentially arranged on a main surface of the substrate in a direction away from the memory cell array, wherein a plurality of bit line patterns are formed on the high-voltage region and the low-voltage region, wherein a plurality of data line patterns are formed on the high-voltage region and the latch region, and wherein widths of the plurality of data line patterns are greater than widths of the bit line patterns. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification