Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors

• US 10,460,817 B2
• Filed: 11/20/2017
• Issued: 10/29/2019
• Est. Priority Date: 07/13/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Li, Xia, Kang, Seung Hyuk, Chen, Wei-Chuan
• Primary Examiner(s): Tran, Uyen B
• Application Number:
  US15/817,474
• Publication Number:
  US 20190019564A1
• Time in Patent Office: 708 Days
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H03K 19/17736 : Structural details of routing resources
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/821 : Device geometry

Abstract

Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

Claims

1. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:

a plurality of word lines configured to receive a multi-bit input vector represented by an input voltage on each word line among the plurality of word lines;

a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;

a plurality of source lines; and

a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of MLC NVM storage circuits; and

each MLC NVM storage circuit among the plurality of MLC NVM storage circuits comprising a plurality of NVM bit cell circuits each configured to store a respective memory state for the corresponding MLC NVM storage circuit;

each NVM bit cell circuit among the plurality of NVM bit cell circuits in a respective MLC NVM storage circuit having a resistance representing a stored memory state, and comprising;

a gate node coupled to a corresponding word line among the plurality of word lines; and

each NVM bit cell circuit configured to couple its resistance to a source line among the plurality of source lines coupled to its respective MLC NVM storage circuit in response to the input voltage applied to the corresponding word line coupled to the gate node.

2. The MLC NVM matrix circuit of claim 1, wherein none of the plurality of word lines are cross-connected to any of the plurality of bit lines.

3. The MLC NVM matrix circuit of claim 1, wherein the resistance of each MLC NVM storage circuit of a respective NVM storage string circuit is coupled to the respective source line forming a multi-bit data vector.

4. The MLC NVM matrix circuit of claim 1, further comprising a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line;

each access transistor among the plurality of access transistors comprising an access gate node coupled to an access line; and

each access transistor among the plurality of access transistors configured to electrically couple the corresponding bit line to the corresponding NVM storage string circuit in response to an access voltage applied to the access gate node.

5. The MLC NVM matrix circuit of claim 4, further comprising a plurality of second access transistors, each second access transistor among the plurality of second access transistors coupled to a corresponding source line among the plurality of source lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits;

each second access transistor among the plurality of second access transistors comprising a second access gate node coupled to a second access line; and

each second access transistor among the plurality of second access transistors configured to electrically couple the corresponding source line to the corresponding NVM storage string circuit in response to an input voltage applied to the second access gate node.

6. The MLC NVM matrix circuit of claim 1, wherein each NVM bit cell circuit among the plurality of NVM bit cell circuits in each MLC NVM storage circuit among the plurality of MLC NVM storage circuits further comprises a semiconductor channel configured to be electrically coupled to the source line to couple the resistance of each NVM bit cell circuit to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node.

7. The MLC NVM matrix circuit of claim 1, wherein a NVM storage string circuit among the plurality of NVM storage string circuits is configured to generate a respective current flowing through a source line among the plurality of source lines coupled to the NVM storage string circuit to a respective output node based on the line voltage applied to the bit line coupled to the NVM storage string circuit and a resistance applied by each of the plurality of MLC NVM storage circuits of the NVM storage string circuit in response to a read activation voltage being applied to the gate node of each of the plurality of NVM bit cell circuits in the respective plurality of MLC NVM storage circuits.

8. The MLC NVM matrix circuit of claim 7, wherein an amplitude of the current flowing through the source line represents a dot product multiplication of a data vector of the MLC NVM storage circuit coupled to the source line, by the multi-bit input vector.

9. The MLC NVM matrix circuit of claim 1, wherein each NVM storage string circuit among the plurality of NVM storage string circuits is configured to generate a respective current flowing through a source line among the plurality of source lines coupled to the NVM storage string circuit to a respective output node based on the line voltage applied to the bit line coupled to the NVM storage string circuit and the resistance applied by each of the plurality of MLC NVM storage circuits of the NVM storage string circuit in response to a read activation voltage being applied to the gate node of each of the plurality of NVM bit cell circuits in the respective plurality of MLC NVM storage circuits.

10. The MLC NVM matrix circuit of claim 7, wherein amplitudes of each respective current among a plurality of currents flowing through the plurality of source lines represents a dot product multiplication of data vectors of the respective MLC NVM storage circuit coupled to the respective source line, by the multi-bit input vector.

11. The MLC NVM matrix circuit of claim 1, wherein one or more MLC NVM storage circuits in a NVM storage string circuit among the plurality of NVM storage string circuits is configured to write a multi-bit memory state based on a write activation voltage applied to the gate node of each of the plurality of NVM bit cell circuits of the respective MLC NVM storage circuits.

12. The MLC NVM matrix circuit of claim 11, wherein the one or more MLC NVM storage circuits in the NVM storage string circuit among the plurality of NVM storage string circuits is further configured to write the multi-bit memory state in response to a read activation voltage different from the write activation voltage applied to the gate node of each of the plurality of NVM bit cell circuits of a number of MLC NVM storage circuits among the plurality of MLC NVM storage circuits not being written.

13. The MLC NVM matrix circuit of claim 1, wherein the plurality of NVM storage string circuits each comprise a plurality of NAND MLC NVM storage circuits each comprising a plurality of NAND NVM bit cell circuits, each NAND MLC NVM storage circuit among the plurality of NAND MLC NVM storage circuits configured to couple its resistance in series on a source line among the plurality of source lines in response to the input voltage applied to the gate node of its respective NAND NVM bit cell circuit among the plurality of NAND NVM bit cell circuits.

14. The MLC NVM matrix circuit of claim 13, wherein each MLC NVM storage circuit in a respective NVM storage string circuit among the plurality of NVM storage string circuits comprises a source node coupled to a drain node of an adjacent MLC NVM storage circuit.

15. The MLC NVM matrix circuit of claim 13, wherein each NAND MLC NVM storage circuit is comprised from a group consisting of:

a NAND MLC NVM flash storage circuit; and

a NAND MLC NVM Ferroelectric (Fe) Field-Effect Transistor (FET) (FeFET) storage circuit.

16. The MLC NVM matrix circuit of claim 1, wherein the plurality of NVM storage string circuits each comprise a plurality of AND MLC NVM storage circuits each comprising a plurality of AND NVM bit cell circuits, each AND MLC NVM storage circuit among the plurality of AND MLC NVM storage circuits configured to couple its resistance in parallel between its corresponding bit line and its corresponding source line in response to the input voltage applied to the gate node of its respective AND NVM bit cell circuit among the plurality of AND NVM bit cell circuits.

17. The MLC NVM matrix circuit of claim 15, wherein each MLC NVM storage circuit in a respective NVM storage string circuit among the plurality of NVM storage string circuits comprises a source node coupled to a drain node of an adjacent MLC NVM storage circuit coupled to a bit line among the plurality of bit lines, and the drain node coupled to the source line coupled to the NVM storage string circuit.

18. The MLC NVM matrix circuit of claim 16, wherein each AND MLC NVM storage circuit is comprised from a group consisting of:

an AND MLC NVM flash storage circuit;

an AND MLC NVM FeFET storage circuit;

an AND MLC NVM magneto-resistive random access memory (MRAM) NVM storage circuit; and

an AND MLC NVM resistive random access memory (RRAM) storage circuit.

19. The MLC NVM matrix circuit of claim 1, wherein the plurality of NVM storage string circuits each comprise a plurality of NOR MLC NVM storage circuits each comprising a plurality of NOR NVM bit cell circuits, each NOR MLC NVM storage circuit among the plurality of NOR MLC NVM storage circuits configured to couple its resistance to a respective source line among the plurality of source lines in response to the input voltage applied to the gate node of its respective NOR NVM bit cell circuit among the plurality of NOR NVM bit cell circuits.

20. The MLC NVM matrix circuit of claim 19, wherein each NOR MLC NVM storage circuit is comprised from a group consisting of:

a NOR MLC NVM flash storage circuit;

a NOR MLC NVM FeFET storage circuit;

a NOR MLC NVM MRAM storage circuit; and

a NOR MLC NVM RRAM storage circuit.

21. The MLC NVM matrix circuit of claim 1 integrated into an integrated circuit (IC).

22. The MLC NVM matrix circuit of claim 1 integrated into a system-on-a-chip (SoC).

23. The MLC NVM matrix circuit of claim 1 integrated into a device selected from a group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a global positioning system (GPS) device;

a mobile phone;

a cellular phone;

a smart phone;

a session initiation protocol (SIP) phone;

a tablet;

a phablet;

a server;

a computer;

a portable computer;

a mobile computing device;

a wearable computing device;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player;

a portable digital video player;

an automobile;

a vehicle component;

avionics systems;

a drone; and

a multicopter.

24. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:

a plurality of means for applying a plurality of input voltages representing a multi-bit input vector;

a plurality of means for applying a plurality of line voltages;

a plurality of means for providing a plurality of output currents representing an output vector; and

a plurality of NVM storage string means each electrically coupled to a corresponding means for applying an input voltage among the plurality of means for applying the plurality of input voltages and a corresponding means for providing an output current among the plurality of means for providing the plurality of output currents, each of the plurality of NVM storage string means, comprising;

a plurality of MLC NV means for storing a multi-bit memory state and each having a resistance representing the stored multi-bit memory state to form a data vector for a corresponding NVM storage string means among the plurality of NVM storage string means; and

each of the plurality of MLC NV means for storing the multi-bit memory state, comprising;

a means for electrically coupling a resistance of a plurality of NV bit means for storing a 1-bit memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents; and

a means for controlling coupling of the resistance of the plurality of NV bit means for storing the 1-bit memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents.

25. A method of performing matrix multiplication in a multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:

applying a line voltage on at least one bit line among a plurality of bit lines coupled to a corresponding NVM storage string circuit among a plurality of NVM storage string circuits, to electrically couple the line voltage to the corresponding NVM storage string circuit coupled to a corresponding bit line among the plurality of bit lines, each NVM storage string circuit among the plurality of NVM storage string circuits comprising a plurality of MLC NVM storage circuits each having a resistance representing a stored multi-bit memory state in the MLC NVM storage circuit to form a data vector for the corresponding NVM storage string circuit;

applying a second line voltage on at least one source line among a plurality of source lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits, to electrically couple the second line voltage to the corresponding NVM storage string circuit coupled to a corresponding source line among the plurality of source lines; and

applying a plurality of input voltages representing a multi-bit input vector on a plurality of word lines, each word line among the plurality of word lines coupled to a corresponding gate node of a NVM bit cell circuit among a plurality of NVM bit cell circuits in each MLC NVM storage circuit among the plurality of MLC NVM storage circuits in each NVM storage string circuit, to electrically couple the MLC NVM storage circuit to the source line to couple the resistance of the MLC NVM storage circuit to the source line.

26. The method of claim 25, further comprising applying an access voltage to a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line, to electrically couple the corresponding bit line to the corresponding NVM storage string circuit.

27. The method of claim 25, further comprising generating a current flowing through a respective source line among the plurality of sources lines to a respective output node coupled to a respective NVM storage string circuit among the plurality of NVM storage string circuits based on a voltage applied to the bit line coupled to the respective NVM storage string circuit and the resistance applied by each of the plurality of MLC NVM storage circuits of the respective NVM storage string circuit in response to a read activation voltage being applied to the gate node of each of the plurality of NVM bit cell circuits in the respective plurality of MLC NVM storage circuits in the respective NVM storage string circuit.

28. The method of claim 27, wherein an amplitude of the current flowing through the source line represents a dot product multiplication of the data vector of the NVM storage string circuit coupled to the source line, by the multi-bit input vector.

29. The method of claim 25, further comprising:

applying the line voltage to a bit line among the plurality of bit lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits;

applying a second line voltage to a source line among the plurality of source lines coupled to the corresponding NVM storage string circuit; and

applying a write activation voltage to the gate node of each of the plurality of NVM bit cell circuits in each of the plurality of MLC NVM storage circuits in the corresponding NVM storage string circuit to write a memory state based on the write activation voltage applied to the gate node of each of the plurality of NVM bit cell circuits in each of the plurality of MLC NVM storage circuits.

30. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix system, comprising:

a first MLC NVM matrix circuit, comprising;

a plurality of first word lines configured to receive a first multi-bit input vector represented by a first input voltage on each first word line among the plurality of first word lines;

a plurality of first bit lines, each first bit line among the plurality of first bit lines configured to receive a corresponding first line voltage;

a plurality of first source lines each coupled to a first output node among a plurality of first output nodes;

a plurality of first NVM storage string circuits, each first NVM storage string circuit among the plurality of first NVM storage string circuits configured to be electrically coupled between a corresponding first bit line among the plurality of first bit lines and a corresponding first source line among the plurality of first source lines each comprising a plurality of first MLC NVM storage circuits;

each first MLC NVM storage circuit among the plurality of first MLC NVM storage circuits comprising a plurality of first NVM bit cell circuits each configured to store a respective memory state for the corresponding first MLC NVM storage circuit;

each first NVM bit cell circuit among the plurality of first NVM bit cell circuits in a respective first MLC NVM storage circuit having a resistance representing a stored memory state, and comprising;

 

a first gate node coupled to a corresponding first word line among the plurality of first word lines; and

each first NVM bit cell circuit configured to couple its resistance to the first source line coupled to its respective first MLC NVM storage circuit in response to an input voltage applied to the corresponding first word line coupled to the first gate node; and

a second MLC NVM matrix circuit, comprising;

a plurality of second word lines each coupled to an output node among the plurality of first output nodes;

a plurality of second bit lines, each second bit line among the plurality of second bit lines configured to receive a corresponding second line voltage;

a plurality of second source lines each coupled to a second output node among a plurality of second output nodes; and

a plurality of second NVM storage string circuits, each second NVM storage string circuit among the plurality of second NVM storage string circuits configured to be electrically coupled between a corresponding second bit line among the plurality of second bit lines and a corresponding second source line among the plurality of second source lines each comprising a plurality of second MLC NVM storage circuits;

each second MLC NVM storage circuit among the plurality of second MLC NVM storage circuits comprising a plurality of second NVM bit cell circuits each configured to store a respective memory state for the corresponding second MLC NVM storage circuit;

each second NVM bit cell circuit among the plurality of second NVM bit cell circuits in a respective second MLC NVM storage circuit having a resistance representing a stored memory state, and comprising;

 

a second gate node coupled to a corresponding second word line among the plurality of second word lines; and

each second NVM bit cell circuit configured to couple its resistance to the second source line coupled to its respective second MLC NVM storage circuit in response to the input voltage applied to the corresponding second word line coupled to the second gate node.