Noise reduction in voltage reference signal

• US 10,460,819 B2
• Filed: 11/30/2016
• Issued: 10/29/2019
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Zanbaghi, Ramin, Das, Tejasvi, Melanson, John L., Thomsen, Axel
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/365,451
• Publication Number:
  US 20180152174A1
• Time in Patent Office: 1,063 Days
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03M 1/0641 the dither being a random signal
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step

Abstract

A variable resistor may be coupled between a reference voltage source and components of an integrated circuit to reduce issues relating to thermal noise from a reference voltage signal generated by the reference voltage source. The variable resistor may be set to a low level during a first time period and a high level during a second time period, in which the time periods correspond to a sampling period of a switched-capacitor circuit. The low resistance time period may allow quick settling of an input reference voltage signal, whereas the high resistance time period may reduce a bandwidth of noise on a sampling capacitor coupled to the reference voltage signal. The variable resistor and switched-capacitor network may be used in an analog-to-digital converter (ADC), such as in audio circuits.

Claims

1. An apparatus, comprising:

a switched-capacitor circuit comprising a reference voltage input node, wherein the switched-capacitor circuit comprises a capacitor comprising a first terminal and a second terminal, and wherein the switched-capacitor circuit further comprises a first switch coupled to the first terminal, and wherein the switched-capacitor circuit further comprises a second switch coupled to the second terminal;

a variable resistor coupled between the reference voltage input node and components of the switched-capacitor circuit; and

a controller configured to adjust the variable resistor, wherein the controller is configured;

to set a resistance value of the variable resistor at a first level during a first time period; and

to set the resistance value of the variable resistor at a second level higher than the first level during a second time period,

wherein the first time period and the second time period are at least part of a first sampling period of the switched-capacitor circuit,

wherein the first switch and the second switch are closed for the duration of the first sampling period, and

wherein the controller is further configured to not short the resistor during a zeroth time period before the first time period, wherein the zeroth time period, the first time period, and the second time period comprise the first sampling period of the switched-capacitor circuit.

2. The apparatus of claim 1, wherein the variable resistor comprises a resistor coupled in parallel with a switch.

3. The apparatus of claim 2, wherein the controller is further configured to operate the switch to change the resistance value of the variable resistor.

4. The apparatus of claim 3, wherein the controller is further configured to short the resistor during the first time period and to not short the resistor during the second time period.

5. The apparatus of claim 1, wherein the zeroth time period has a duration selected to reduce kickback from the switched-capacitor circuit to the reference voltage input node, and wherein the second time period has a duration selected to reduce a thermal noise contribution from a reference on a sampling capacitor of the switched-capacitor circuit during a sampling phase.

6. The apparatus of claim 1, wherein the controller is further configured to set the resistance value of the variable resistor at a third level higher than the first level during a zeroth time period before the first time period.

7. An apparatus, comprising:

a switched-capacitor circuit comprising a reference voltage input node, wherein the switched-capacitor circuit comprises a capacitor comprising a first terminal and a second terminal, and wherein the switched-capacitor circuit further comprises a first switch coupled to the first terminal, and wherein the switched-capacitor circuit further comprises a second switch coupled to the second terminal;

a variable resistor coupled between the reference voltage input node and components of the switched-capacitor circuit; and

a controller configured to adjust the variable resistor, wherein the controller is configured;

to set a resistance value of the variable resistor at a first level during a first time period; and

to set the resistance value of the variable resistor at a second level higher than the first level during a second time period,

to not short the resistor during a zeroth time period before the first time period, wherein the zeroth time period, the first time period, and the second time period comprise the first sampling period of the switched-capacitor circuit, and

wherein the first switch and the second switch are closed for at least the duration of the first time period and the second time period of the first sampling period, wherein the switched-capacitor circuit is part of an analog-to-digital converter (ADC), and the reference voltage input node is coupled to an on-chip reference voltage generator.

8. A method of reducing noise coming from an on-chip reference in a switched-capacitor circuit, wherein the switched-capacitor circuit comprises a capacitor comprising a first terminal and a second terminal, and wherein the switched-capacitor circuit further comprises a first switch coupled to the first terminal, and wherein the switched-capacitor circuit further comprises a second switch coupled to the second terminal, the method comprising:

controlling a variable resistor coupled between the switched-capacitor circuit and the on-chip reference by performing steps comprising;

setting a resistance value of the variable resistor at a first level during a first time period of a first sampling period of the switched-capacitor circuit; and

setting the resistance value of the variable resistor at a second level higher than the first level during a second time period of the switched-capacitor circuit,

wherein the first time period and the second time period are at least part of a first sampling period of the switched-capacitor circuit,

wherein the first switch and the second switch are closed for the duration of the first sampling period, and

wherein the step of controlling the variable resistor further comprises the step of setting the resistance value of the variable resistor at a third level lower than the second level during a zeroth time period before the first time period.

9. The method of claim 8, wherein the step of controlling the variable resistor comprises controlling a switch coupled in parallel with a resistor.

10. The method of claim 9, wherein the step of setting the resistance value of the variable resistor at the first level comprises shorting the resistor with the switch, and wherein the step of setting the resistance value of the variable resistor at the second level comprises not shorting the resistor with the switch.

11. The method of claim 8, wherein the zeroth time period has a duration selected to reduce feedback from the switched-capacitor circuit to the on-chip reference, and wherein the second time period has a duration selected to reduce thermal noise in a received reference voltage level from the on-chip reference.

12. The method of claim 8, wherein the step of controlling the variable resistor is performed during conversion of an input analog signal to an output digital signal.

13. A method of reducing noise coming from an on-chip reference in a switched-capacitor circuit, comprising:

providing a first switch and a second switch and a capacitor coupled through a first terminal and a second terminal to the first switch and the second switch, respectively, to form the switched-capacitor circuit;

coupling an artifact reduction network (ARN) between the switched-capacitor circuit and an output of a buffer of the on-chip reference, wherein the ARN is transparent during a first time period of a sampling phase to not affect settling accuracy and is activated during another portion of the sampling phase to limit sampling network bandwidth during a second time period of the sampling phase,

wherein the first switch and the second switch are closed for the duration of the first sampling period; and

controlling the artifact reduction network (ARN) to set the resistance value of the artifact reduction network (ARN) at a third level lower than the second level during a zeroth time period before the first time period.

14. The method of claim 13, wherein the step of coupling the artifact reduction network (ARN) comprises coupling a switch in parallel with a resistor between the switched-capacitor circuit and the output of the buffer of the on-chip reference.

15. The method of claim 14, further comprising:

controlling the artifact reduction network (ARN) to set a resistance value of the artifact reduction network (ARN) at a first level during a first time period of a first sampling period of the switched-capacitor circuit such that the artifact reduction network (ARN) is transparent; and

controlling the artifact reduction network (ARN) to activate the artifact reduction network (ARN) by setting the resistance value of the artifact reduction network (ARN) at a second level higher than the first level during a second time period of the switched-capacitor circuit.

16. The method of claim of claim 15, wherein the step of controlling the artifact reduction network (ARN) to set the resistance value of the artifact reduction network (ARN) at the first level comprises controlling the switch to short the resistor.