Sorting non-volatile memories

• US 10,460,825 B2
• Filed: 01/28/2016
• Issued: 10/29/2019
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Christensen, Jeffrey W., Christensen, Phillip E., Moore, Daniel E., Sater, Antoine G., Yoon, Jung H.
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US15/008,843
• Publication Number:
  US 20170221582A1
• Time in Patent Office: 1,370 Days
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

Claims

1. A method, executed by one or more processors, for sorting non-volatile random access memories (NVRAMS), the method comprising:

testing, via the one or more processors, a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS;

determining, via the one or more processors, a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data;

physically separating, via the one or more processors, the plurality of NVRAMS into routing groups based on the trend in the failure metric as a function of testing cycles; and

physically routing, via the one or more processors, the routing groups within a manufacturing environment.

2. The method of claim 1, wherein determining the trend in the failure metric comprises determining an extrapolated value for the failure metric.

3. The method of claim 1, wherein determining the trend in the failure metric comprises determining a derivative for the failure metric.

4. The method of claim 1, wherein separating the plurality of NVRAMS into groups based on the trend in the failure metric comprises determining whether the trend in the failure metric for a selected NVRAM deviates significantly from typical trends in the failure metric for the plurality of NVRAMS.

5. The method of claim 1, further comprising repetitively conducting testing sessions until a selected confidence level is attained for one or more separation metrics derived from the failure metric data.

6. The method of claim 1, further comprising weighting the failure metric according to the testing session.

7. The method of claim 1, wherein the failure metric is selected from the group consisting of a grown bad blocks count, a total bad blocks count, a bit error rate, and an error count.

8. The method of claim 1, wherein the groups comprise at least one of a scrap group, a rework group, an acceptable quality group, and an exceptional quality group.

9. The method of claim 1, wherein the failure metric data is used to determine a faulty device location.

10. The method of claim 1, further comprising dynamically adjusting a separation metric over the plurality of testing sessions.

11. A computer system comprising:

one or more computers;

one or more computer readable storage media and program instructions stored on the one or more computer readable storage media for execution by at least one of the computers, the program instructions comprising instructions executable by a computer to perform;

testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS;

determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data;

physically separating the plurality of NVRAMS into routing groups based on the trend in the failure metric as a function of testing cycles; and

physically routing the routing groups within a manufacturing environment.