Stress relieving semiconductor layer

• US 10,460,952 B2
• Filed: 06/29/2018
• Issued: 10/29/2019
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Sun, Wenhong, Jain, Rakesh, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US16/022,939
• Publication Number:
  US 20180323071A1
• Time in Patent Office: 487 Days
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66075 of devices having semiconductor bodies comprising group 14 or group 13/15 materials comprising semiconducting carbon H01L29/66015; comprising crystalline silicon carbide H01L29/66053
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Claims

1. A structure comprising:

a substrate;

a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands; and

a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

2. The structure of claim 1, where in the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

3. The structure of claim 1, wherein the characteristic size of the plurality of cavities is in a range of approximately ten nanometers to approximately four thousand nanometers.

4. The structure of claim 1, further comprising a semiconductor layer immediately adjacent to the cavity containing layer, wherein the semiconductor layer contains no large scale cavities.

5. The structure of claim 4, wherein the semiconductor layer comprises Al_xGa_1-xN, wherein 0<

x<

1.

6. The structure of claim 5, wherein x>

0.8.

7. The structure of claim 1, wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle.

8. The structure of claim 7, wherein the angle is equal to or greater than 0.6 degrees and equal to or less than 3 degrees.

9. The structure of claim 1, further comprising a second nucleation layer located directly on the nucleation layer including the plurality of nucleation islands, wherein the nucleation layer including the plurality of nucleation islands is partially-etched.

10. The structure of claim 1, wherein the substrate is nano-patterned.

11. A device comprising:

a substrate;

a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands;

a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers; and

a semiconductor layer located over the cavity containing layer, wherein the semiconductor layer contains no cavities.

12. The device of claim 11, where in the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

13. The device of claim 11, wherein the characteristic size of the plurality of cavities is in a range of approximately ten nanometers to approximately four thousand nanometers.

14. The device of claim 11, wherein the semiconductor layer comprises Al_xGa_1-xN, wherein 0<

x<

1.

15. The device of claim 14, wherein x>

0.8.

16. The device of claim 11, wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle equal to or greater than 0.6 degrees and equal to or less than 3 degrees.

17. The device of claim 11, further comprising a second nucleation layer located directly on the nucleation layer including the plurality of nucleation islands, wherein the nucleation layer including the plurality of nucleation islands is partially-etched.

18. The device of claim 11, wherein the substrate is nano-patterned.

19. A method comprising:

fabricating a semiconductor structure, wherein the fabricating includes;

growing a nucleation layer on a substrate, wherein the nucleation layer is formed of a plurality of nucleation islands;

forming a cavity containing layer over the nucleation layer, wherein the cavity containing layer has a thickness greater than two monolayers and a plurality of cavities; and

forming a semiconductor layer directly on the cavity containing layer, wherein the semiconductor layer comprises Al_xGa_1-xN, wherein 0.8<

x<

1.

20. The method of claim 19, wherein the fabricating further comprises:

partially etching the nucleation layer and the substrate at a temperature of at least 1000 degrees Celsius in an H₂ ambient, such that the substrate is nano-patterned; and

growing a second nucleation layer directly on the partially etched nucleation layer and the nano-patterned substrate.