Formation of semiconductor devices with dual trench isolations

• US 10,460,982 B1
• Filed: 06/14/2018
• Issued: 10/29/2019
• Est. Priority Date: 06/14/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Juntao, Cheng, Kangguo, Lee, Choonghyun, Xu, Peng
• Primary Examiner(s): Blum, David S
• Application Number:
  US16/008,431
• Time in Patent Office: 502 Days
• Field of Search: 438427, 438424, 257510
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method for fabricating a semiconductor device with dual trench isolations includes forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors, forming a first shallow trench located between transistors of the first array and a second shallow trench located between transistors of the second array, and forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

Claims

1. A method for fabricating a semiconductor device with dual trench isolations, comprising:

forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors;

forming a first shallow trench located between transistors within the first array and a second shallow trench located between transistors within the second array; and

forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

2. The method of claim 1, wherein the single dielectric material fill process includes forming dielectric material in the deep trench and the first and second shallow trenches, and planarizing the dielectric material.

3. The method of claim 1, further comprising forming a trench liner in the deep trench and the first and second trenches, wherein the DTI region and the first and second STI regions are formed on the trench liner.

4. The method of claim 1, further comprising:

forming a first pad dielectric layer on a semiconductor-on-insulator (SOT) substrate, the SOT substrate including a base substrate, an insulator layer formed on the base substrate, and an SOI layer formed on the insulator layer;

forming a second pad dielectric layer on the first pad dielectric layer; and

patterning masks on the second pad dielectric layer.

5. The method of claim 4, wherein the first pad dielectric layer includes a pad oxide layer and the second pad dielectric layer includes a pad nitride layer.

6. The method of claim 4, further comprising:

performing a first etch process to remove material up to the first pad dielectric layer;

removing the masks;

forming a dielectric liner on the first and second pad dielectric layers;

performing a second etch process by removing material to a depth in the base substrate to form the deep trench;

performing a third etch process by removing material up to the insulator layer to form the first and second shallow trenches; and

removing the dielectric liner.

7. The method of claim 6, wherein the dielectric liner is removed prior performing the third etch process to form the first and second shallow trenches.

8. The method of claim 4, further comprising:

performing a first etch process by removing material up to the insulator layer to form the first and second shallow trenches;

removing the masks;

forming a dielectric liner on the insulator layer, the SOI layer, and the first and second pad dielectric layers; and

performing a second etch process by removing material to a depth in the base substrate to form the deep trench; and

removing the dielectric liner.

9. The method of claim 4, further comprising recessing the DTI region and the first and second STI regions, and removing the first and second pad dielectric layers.

10. The method of claim 9, further comprising forming the first and second arrays of transistors.

11. The method of claim 10, further comprising forming a first well within the base substrate in the first region and a second well within the base substrate in the second region prior to forming the first and second arrays of transistors.

12. A method for fabricating a semiconductor device with dual trench isolations, comprising:

forming a first pad dielectric layer on a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a base substrate, an insulator layer formed on the base substrate, and an SOI layer formed on the insulator layer;

forming a second pad dielectric layer on the first pad dielectric layer;

patterning masks on the second pad dielectric layer;

forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors by removing material to a depth in the base substrate;

forming a first shallow trench located between transistors within the first array and a second shallow trench located between transistors within the second array by removing material up to the insulator layer; and

forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench, the single dielectric material fill process including forming dielectric material in the deep trench and the first and second shallow trenches, and planarizing the dielectric material.

13. The method of claim 12, further comprising forming a trench liner in the deep trench and the first and second trenches, wherein the DTI region and the first and second STI regions are formed on the trench liner.

14. The method of claim 12, wherein the first pad dielectric layer includes a pad oxide layer and the second pad dielectric layer includes a pad nitride layer.

15. The method of claim 12, further comprising:

performing a first etch process to remove material up to the first pad dielectric layer;

removing the masks;

forming a dielectric liner on the first and second pad dielectric layers;

performing a second etch process to form the deep trench;

performing a third etch process to form the first and second shallow trenches; and

removing the dielectric liner.

16. The method of claim 15, wherein the dielectric liner is removed prior to forming the first and second shallow trenches.

17. The method of claim 12, further comprising:

performing a first etch process to form the first and second shallow trenches;

removing the masks;

forming a dielectric liner on the insulator layer, the SOI layer, and the first and second pad dielectric layers; and

performing a second etch process to form the deep trench; and

removing the dielectric liner.

18. The method of claim 12, further comprising recessing the DTI region and the first and second STI regions, removing the first and second pad dielectric layers, and forming the first and second arrays of transistors.

19. The method of claim 18, further comprising forming a first well within the base substrate in the first region and a second well within the base substrate in the second region prior to forming the first and second arrays of transistors.

20. A semiconductor device with dual trench isolations, comprising:

a first device region disposed on a base substrate;

a second device region disposed on the base substrate; and

a deep trench isolation (DTI) region separating the first and second device regions;

the first and second device regions each including;

a well;

an insulator layer disposed on the well;

semiconductor-on-insulator (SOI) layers disposed on the insulator layer;

an array of transistors disposed on respective ones of the SOI layers; and

at least one shallow trench isolation (STI) region separating adjacent ones of transistors within the array.