Semiconductor wafer and method of probe testing

• US 10,461,000 B2
• Filed: 02/28/2018
• Issued: 10/29/2019
• Est. Priority Date: 08/08/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Seddon, Michael J., Lee, Heng Chen
• Primary Examiner(s): Nguyen, Niki H
• Application Number:
  US15/907,931
• Publication Number:
  US 20180190552A1
• Time in Patent Office: 608 Days
• Field of Search: 257 48, 257E23179, 257E21521, 257E21524, 438113, 438 15
• CPC Class Codes: G01R 31/2865 Holding devices, e.g. chucks; Handlers or transport devices having contacts G01R31/2863
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2221/68304 using temporarily an auxiliary support

Abstract

A semiconductor test system has a wafer holder with a tape portion and one or more openings through the tape portion. A semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test. A plurality of bumps can be formed on the semiconductor wafer. The semiconductor wafer can be a stacked semiconductor wafer. A conductive trace can be formed on the tape portion and the semiconductor wafer probe tested through the conductive trace. An active surface or non-active surface of the semiconductor wafer can be oriented toward the tape portion. The electrical connection to the semiconductor wafer through the opening in the tape portion can be a ground reference node. A conductive layer is formed over a non-active surface of the semiconductor wafer.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer;

providing a wafer holder including a tape portion with an opening through the tape portion;

mounting the semiconductor wafer over the opening in the tape portion of the wafer holder; and

providing an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.

2. The method of claim 1, further including forming a plurality of bumps over the semiconductor wafer.

3. The method of claim 1, wherein providing the semiconductor wafer includes providing a stacked semiconductor wafer.

4. The method of claim 1, further including forming a conductive trace over the tape portion.

5. The method of claim 1, further including forming the opening through the tape portion after mounting the tape portion to the wafer holder.

6. The method of claim 1, further including forming the opening through the tape portion prior to mounting the tape portion to the wafer holder.

7. An apparatus for probe testing a semiconductor device, comprising:

a semiconductor wafer; and

a wafer holder including a tape portion with an opening through the tape portion, wherein the semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.

8. The apparatus of claim 7, further including a plurality of bumps formed over the semiconductor wafer.

9. The apparatus of claim 7, wherein the semiconductor wafer includes a stacked semiconductor wafer.

10. The apparatus of claim 7, further including a conductive trace formed over the tape portion.

11. The apparatus of claim 7, wherein an active surface of the semiconductor wafer is oriented toward the tape portion.

12. The apparatus of claim 7, wherein a non-active surface of the semiconductor wafer is oriented toward the tape portion.

13. The apparatus of claim 7, wherein the electrical connection to the semiconductor wafer through the opening in the tape portion is a ground reference node.

14. An apparatus for probe testing a semiconductor device, comprising:

a semiconductor wafer; and

a wafer holder including a tape portion; and

a conductive trace formed on the tape portion, wherein the semiconductor wafer is mounted over the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the conductive trace during probe test.

15. The apparatus of claim 14, further including a plurality of bumps formed over the semiconductor wafer.

16. The apparatus of claim 14, wherein the semiconductor wafer includes a stacked semiconductor wafer.

17. The apparatus of claim 14, wherein an active surface of the semiconductor wafer is oriented toward the tape portion.

18. The apparatus of claim 14, wherein a non-active surface of the semiconductor wafer is oriented toward the tape portion.

19. The apparatus of claim 14, further including an opening through the tape portion.

20. The apparatus of claim 14, further including a conductive layer over a non-active surface of the semiconductor wafer.