3DIC packaging with hot spot thermal management features

• US 10,461,009 B2
• Filed: 11/30/2018
• Issued: 10/29/2019
• Est. Priority Date: 12/04/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hung, Wensen, Huang, Szu-Po, Lee, Hsiang-Fan, Chen, Kim Hong, Wu, Chi-Hsi, Jeng, Shin-Puu
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US16/206,903
• Publication Number:
  US 20190096781A1
• Time in Patent Office: 333 Days
• Field of Search: 257686, 257777, 257707
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29294 with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/33519 including layer connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92225 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/04 : characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/1679 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Claims

1. A package comprising:

a die stack comprising;

a plurality of first dies; and

a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and

a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises;

a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and

a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line.

2. The package of claim 1, further comprising a heat dissipation feature adhered to the package substrate by an adhesive, wherein the conductive line is thermally connected to the heat dissipation feature through the TIM.

3. The package of claim 2, wherein the heat dissipation feature is adhered to the package substrate by an adhesive having a lower thermal conductivity than the TIM.

4. The package of claim 3, wherein the adhesive encircles the second portion of the conductive line in a top down view.

5. The package of claim 1, wherein the conductive line is a signal line, a power line, or a ground line.

6. The package of claim 1, wherein the conductive line is a dummy feature.

7. The package of claim 1, wherein the second portion of the conductive line overlaps and encircles the die stack in a top down view.

8. The package of claim 1, wherein the second die comprises a first logic core and a second logic core, wherein the second portion of the conductive line overlaps the first logic core in a top down view, wherein a second conductive line overlaps the second logic core in the top down view, wherein the solder resist does not cover a first portion of the second conductive line, and wherein the conductive line is disconnected from the second conductive line.

9. The package of claim 8, wherein the first logic core is larger than the second logic core, and wherein the second portion of the conductive line has a larger surface area than the first portion of the second conductive line.

10. A package comprising:

a die stack bonded to a first side of a package substrate, wherein the die stack is electrically connected to a conductive layer of the package substrate, and wherein the die stack comprises;

a first die; and

one or more second dies over and electrically connected to the first die;

a first material on the first side of the package substrate and physically contacting a first region of the conductive layer, wherein the first material has a thermal conductivity between 3 W/m·

K and 50 W/m·

K, wherein the first material is disposed directly under the one or more second dies and extends along a sidewall of the first die; and

a second material on the first side of the package substrate and physically contacting a second region of the conductive layer, wherein the second material has a thermal conductivity between 3 W/m·

K and 50 W/m·

K, wherein the first material and the second material are physically separated, and wherein the conductive layer thermally connects the first material to the second material.

11. The package of claim 10 further comprising a heat dissipation feature attached to the front side of the package substrate using an adhesive having a lower thermal conductivity than the first material, wherein the heat dissipation feature is in physical contact with the second material.

12. The package of claim 11, wherein the adhesive is disposed on an opposing side of the second material as the first material.

13. The package of claim 10 further comprising a solder resist covering a portion of the conductive layer, wherein the first material and the second material each extend through the solder resist to physically contact the conductive layer.

14. The package of claim 10, wherein the first material is a thermal interface material.

15. The package of claim 10 further comprising a passive device between the first material and the second material.

16. A package comprising:

a first die stack comprising;

a bottom die; and

a top die over and bonded to the bottom die;

a package substrate bonded to the first die stack, wherein a first conductive line in the package substrate is electrically connected to the first die stack;

a first thermal interface material (TIM) on a same surface of the package substrate as the first die stack, wherein the first TIM extends through a solder resist to contact the first conductive line, and wherein the first conductive line thermally connects the first die stack to the first TIM; and

a first heat dissipation feature contacting the first TIM.

17. The package of claim 16 further comprising a second die stack, wherein the first die stack and the second die stack have different heights.

18. The package of claim 16, further comprising a second TIM on a top surface of the bottom die, wherein the second TIM contacts the first heat dissipation feature.

19. The package of claim 16, wherein a second conductive line in the package substrate is electrically connected to the first conductive line by a conductive via, wherein the second conductive line thermally connects the first die stack to the first TIM.

20. The package of claim 16 further comprising:

a third TIM on a top surface of the top die; and

a second heat dissipation feature contacting the third TIM, wherein the second heat dissipation feature is attached to the first heat dissipation feature by a second adhesive layer.