Semiconductor device including via plug and method of forming the same
First Claim
Patent Images
1. A semiconductor device, comprising:
- a lower insulating layer on a substrate;
a conductive pattern in the lower insulating layer;
a middle insulating layer on the lower insulating layer and the conductive pattern;
a via control region in the middle insulating layer, the via control region having a lower etch rate than the middle insulating layer;
an upper insulating layer on the middle insulating layer and the via control region; and
a via plug passing through the via control region and connected to the conductive pattern.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.
-
Citations
20 Claims
-
1. A semiconductor device, comprising:
-
a lower insulating layer on a substrate; a conductive pattern in the lower insulating layer; a middle insulating layer on the lower insulating layer and the conductive pattern; a via control region in the middle insulating layer, the via control region having a lower etch rate than the middle insulating layer; an upper insulating layer on the middle insulating layer and the via control region; and a via plug passing through the via control region and connected to the conductive pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A semiconductor device, comprising:
-
a lower insulating layer on a substrate; a plurality of conductive patterns in the lower insulating layer; a middle insulating layer on the lower insulating layer and the conductive patterns; a plurality of via control regions in the middle insulating layer, the via control regions being arranged between the plurality of conductive patterns, and the via control regions having a lower porosity than the middle insulating layer; an upper insulating layer on the middle insulating layer and the via control regions; and a via plug between the via control regions and connected to one selected from among the conductive patterns.
-
-
19. A semiconductor device, comprising:
-
a lower insulating layer on a substrate; a conductive pattern in the lower insulating layer; a middle insulating layer on the lower insulating layer and the conductive pattern; a via control region formed in the middle insulating layer, the via control region including a material having a lower etch rate than the middle insulating layer; an upper insulating layer on the middle insulating layer and the via control region; a via plug passing through the via control region and connected to the conductive pattern; and an upper interconnection in the upper insulating layer and connected to the via plug. - View Dependent Claims (20)
-
Specification