Method for patterning a power metallization layer, electronic device and method for processing an electronic device

• US 10,461,031 B2
• Filed: 06/08/2018
• Issued: 10/29/2019
• Est. Priority Date: 06/09/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Fischer, Petra, Schlaminger, Johanna, Voerckel, Monika Cornelia, Zorn, Peter
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US16/003,687
• Publication Number:
  US 20180358299A1
• Time in Patent Office: 508 Days
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

According to various embodiments, a method for processing an electronic device may include: forming a patterned hard mask layer over a power metallization layer, the patterned hard mask layer exposing at least one surface region of the power metallization layer; and patterning the power metallization layer by wet etching of the exposed at least one surface region of the power metallization layer.

Claims

1. A method for processing an electronic device, the method comprising:

forming a patterned hard mask layer over a copper power metallization layer, the patterned hard mask layer exposing a major outer surface of the copper power metallization layer; and

patterning the copper power metallization layer by wet etching of the exposed major surface of the copper power metallization layer, wherein forming the patterned hard mask layer comprises forming a patterned alumina layer with a thickness less than 15 nm, wherein the copper power metallization layer has a thickness greater than 5 μ

m.

2. The method according to claim 1, wherein forming the patterned hard mask layer comprises forming at least one layer of the following group of layers:

a patterned metal layer,

a pattered nitride layer,

a patterned oxide layer, or

a patterned oxynitride layer.

3. The method according to claim 1, further comprising:

partially removing the patterned hard mask layer after patterning the power metallization layer.

4. The method according to claim 1, wherein forming the patterned hard mask layer comprises:

depositing a hard mask layer over the copper power metallization layer;

forming a patterned photoresist mask layer over the hard mask layer, the patterned photoresist mask layer exposing a major surface of the hard mask layer; and

using the patterned photoresist mask layer as an etch mask, etching the hard mask layer to expose the major outer surface of the copper power metallization layer.

5. The method according to claim 1, wherein patterning the copper power metallization layer comprises exposing a sidewall, the sidewall having a slope greater than 60°

.

6. The method according to claim 1, further comprising forming a contact structure over the patterned hard mask layer by partially removing and/or modifying the patterned hard mask layer in a contact region between the contact structure and the patterned copper metallization layer.

7. A method for processing an electronic device, the method comprising:

forming a patterned hard mask layer over a copper power metallization layer, the patterned hard mask layer exposing a major outer surface of the copper power metallization layer;

patterning the copper power metallization layer by wet etching of the exposed major surface of the copper power metallization layer; and

forming a barrier layer, wherein the copper power metallization layer is formed over the barrier layer, and wherein a surface of the barrier layer is exposed after the patterning the copper power metallization layer, wherein the barrier layer comprises titanium and/or tungsten.

8. The method of claim 7, wherein forming the patterned hard mask layer comprises forming a patterned alumina layer with a thickness less than 15 nm, wherein the copper power metallization layer has a thickness greater than 5 μ

m.

9. A method for patterning a power metallization layer, the method comprising:

forming a hard mask layer over the power metallization layer;

forming a patterned soft mask layer over the hard mask layer and patterning the hard mask layer by wet etching to expose a major outer surface of the power metallization layer; and

patterning the power metallization layer by wet etching of the exposed major outer surface of the power metallization layer using an etch mask comprising the patterned hard mask layer and the patterned soft mask layer.

10. The method according to claim 9, wherein a contact structure is formed over the patterned hard mask layer to electrically couple the contact structure and the patterned power metallization layer.

11. The method according to claim 9, wherein modifying the patterned hard mask layer comprises reducing a metal in the patterned hard mask layer.

12. The method according to claim 9, wherein forming the hard mask layer comprises depositing a alumina layer with a thickness less than 15 nm, wherein the power metallization layer comprises a copper layer having a thickness greater than 5 μ

m.

13. The method according to claim 9, wherein the hard mask layer comprises titanium, tantalum, hafnium, boron, silicon, or carbon.

14. The method according to claim 9, further comprising forming a barrier layer, wherein the power metallization layer is formed over the barrier layer, and wherein a surface of the barrier layer is exposed after the patterning the power metallization layer, wherein the barrier layer comprises titanium and/or tungsten.

15. The method according to claim 9, wherein patterning the power metallization layer comprises exposing a sidewall, the sidewall having a slope greater than 60°

.

16. An electronic device comprising:

an electronic structure;

a copper contact structure electrically contacting the electronic structure, the copper contact structure having a thickness greater than 5 μ

m; and

an alumina protection layer having a thickness less than 15 nm and disposed over the copper contact structure, wherein the copper contact structure has a sidewall with a slope greater than 60°

.

17. The electronic device according to claim 16, further comprising a contact structure electrically coupled to the copper contact structure disposed over the alumina protection layer.

18. The electronic device according to claim 16,

wherein the copper contact structure has an aspect ratio of greater than 0.5.

19. The electronic device according to claim 16, wherein the copper contact structure has a feature size less than 10 μ

m.

20. The electronic device according to claim 16, further comprising a barrier layer, wherein the copper contact structure is disposed over the barrier layer, and wherein the barrier layer comprises titanium and/or tungsten.