Thermally enhanced package to reduce thermal interaction between dies

• US 10,461,067 B2
• Filed: 10/31/2017
• Issued: 10/29/2019
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Patel, Janak, Iyer, Subramanian Srikanteswara, Berger, Daniel
• Primary Examiner(s): Garces, Nelson
• Application Number:
  US15/799,600
• Publication Number:
  US 20180068993A1
• Time in Patent Office: 728 Days
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

Claims

1. A device comprising:

integrated circuit (IC) chips, comprising a logic chip and at least one memory stack adjacent the logic chip, attached to an upper surface of a substrate;

a lid thermally connected to an upper surface of the IC chips by a first thermal interface material (TIM1);

a slit formed through the lid by punch and die at a boundary between the logic chip and each memory stack;

a heat sink thermally connected to the lid by a second thermal interface material (TIM2);

at least one co-axial hole formed in the lid and the heat sink; and

a vertical heat pipe extending through each co-axial hole for direct thermal contact with an IC chip and the heat sink.

2. The device according to claim 1, wherein a length of the vertical heat pipes equals a sum of a thickness of TIM1.

3. The device according to claim 2, wherein a thickness of the lid, a thickness of TIM2, and a height of the heat sink, a diameter of each vertical heat pipe ranges from 1 millimeter (mm) to a width of the IC chip with which it is in thermal contact.

4. The device according to claim 3, wherein the vertical heat pipes have conductivity in only one direction.

5. A device comprising:

integrated circuit (IC) chips, comprising a logic chip and at least one memory stack adjacent the logic chip, attached to an upper surface of a substrate;

a lid thermally connected to an upper surface of the IC chips by a first thermal interface material (TIM1);

a slit formed through the lid by punch and die at a boundary between the logic chip and each memory stack; and

a heat sink formed over the lid, the heat sink having vertical pipes penetrating the heat sink and reaching the IC chips and the vertical pipes in direct thermal contact with the IC chips and heat sink,

wherein the vertical heat pipes extend through co-axial holes in the lid and the heat sink.

6. The device according to claim 5, wherein the vertical heat pipes have conductivity in only one direction.

7. The device according to claim 5, wherein the vertical heat pipes comprise copper (Cu).