Super-self-aligned contacts and method for making the same

• US 10,461,081 B2
• Filed: 11/13/2017
• Issued: 10/29/2019
• Est. Priority Date: 12/13/2007
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Smayling, Michael C.
• Primary Examiner(s): Diallo, Mamadou L
• Application Number:
  US15/811,538
• Publication Number:
  US 20180083003A1
• Time in Patent Office: 715 Days
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

Claims

1. A semiconductor device, comprising:

a first linear gate structure;

a second linear gate structure located next to the first linear gate structure, the second linear gate structure separated from the first linear gate structure by a gate pitch, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor;

a third linear gate structure located next to the second linear gate structure, the third linear gate structure separated from the second linear gate structure by the gate pitch, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor;

a fourth linear gate structure located next to the third linear gate structure, the fourth linear gate structure separated from the third linear gate structure by the gate pitch, the fourth linear gate structure forming a third PMOS transistor and a third NMOS transistor;

a fifth linear gate structures located next to the fourth linear gate structure, the fifth linear gate structure separated from the fourth linear gate structure by the gate pitch;

a first gate contact physically connected to the second linear gate structure at a location between the first PMOS transistor and the first NMOS transistor;

a second gate contact physically connected to the third linear gate structure at a location between the second PMOS transistor and the second NMOS transistor; and

a third gate contact physically connected to the fourth linear gate structure at a location between the third PMOS transistor and the third NMOS transistor.

2. The semiconductor device as recited in claim 1, wherein each of the first, second, third, fourth, and fifth linear gate structures extends lengthwise in a first direction, wherein the first gate contact is offset in the first direction from the second gate contact.

3. The semiconductor device as recited in claim 2, wherein the second gate contact is offset in the first direction from the third gate contact.

4. The semiconductor device as recited in claim 3, wherein the first gate contact is offset in the first direction from the third gate contact.

5. The semiconductor device as recited in claim 1, wherein each of the first, second, third, fourth, and fifth linear gate structures extends lengthwise in a first direction, wherein the second linear gate structure has a width measured in a second direction perpendicular to the first direction, wherein the first gate contact has a width measured in the second direction, wherein the width of the first gate contact is substantially equal to the width of the second linear gate structure.

6. The semiconductor device as recited in claim 5, wherein the third linear gate structure has a width measured in the second direction, wherein the second gate contact has a width measured in the second direction, wherein the width of the second gate contact is substantially equal to the width of the third linear gate structure.

7. The semiconductor device as recited in claim 6, wherein the fourth linear gate structure has a width measured in the second direction, wherein the third gate contact has a width measured in the second direction, wherein the width of the third gate contact is substantially equal to the width of the fourth linear gate structure.

8. The semiconductor device as recited in claim 7, wherein each of the first, second, and third gate contacts has a substantially equal length as measured in the first direction.

9. The semiconductor device as recited in claim 8, wherein the widths of the second, third, and fourth linear gate structures are substantially equal.

10. The semiconductor device as recited in claim 1, wherein each of the first, second, third, fourth, and fifth linear gate structures extends lengthwise in a first direction, wherein a first end of the second linear gate structure is substantially aligned in the first direction with a first end of the third linear gate structure.

11. The semiconductor device as recited in claim 10, wherein a first end of the fourth linear gate structure is substantially aligned in the first direction with a first end of the third linear gate structure.

12. The semiconductor device as recited in claim 11, wherein a second end of the second linear gate structure is substantially aligned in the first direction with a second end of the third linear gate structure.

13. The semiconductor device as recited in claim 12, wherein a second end of the fourth linear gate structure is substantially aligned in the first direction with a second end of the third linear gate structure.

14. The semiconductor device as recited in claim 1, wherein the first linear gate structure does not form a gate electrode of a transistor.

15. The semiconductor device as recited in claim 14, wherein the fifth linear gate structure does not form a gate electrode of a transistor.

16. The semiconductor device as recited in claim 1, further comprising:

a first p-type diffusion region formed between the first linear gate structure and the first PMOS transistor;

a second p-type diffusion region formed to extend from the first PMOS transistor to the second PMOS transistor;

a third p-type diffusion region formed to extend from the second PMOS transistor to the third PMOS transistor; and

a fourth p-type diffusion region formed between the third PMOS transistor and the fifth linear gate structure.

17. The semiconductor device as recited in claim 16, further comprising:

a first n-type diffusion region formed between the first linear gate structure and the first NMOS transistor;

a second n-type diffusion region formed to extend from the first NMOS transistor to the second NMOS transistor;

a third n-type diffusion region formed to extend from the second NMOS transistor to the third NMOS transistor; and

a fourth n-type diffusion region formed between the third NMOS transistor and the fifth linear gate structure.

18. The semiconductor device as recited in claim 17, further comprising:

a first diffusion contact physically connected to the first p-type diffusion region;

a second diffusion contact physically connected to the second p-type diffusion region;

a third diffusion contact physically connected to the third p-type diffusion region;

a fourth diffusion contact physically connected to the fourth p-type diffusion region;

a fifth diffusion contact physically connected to the first n-type diffusion region; and

a sixth diffusion contact physically connected to the fourth n-type diffusion region.

19. The semiconductor device as recited in claim 18, wherein the second diffusion contact is substantially equally spaced from each of the second linear gate structure and the third linear gate structure.

20. The semiconductor device as recited in claim 19, wherein the fourth diffusion contact is substantially equally spaced from each of the fourth linear gate structure and the fifth linear gate structure.

21. The semiconductor device as recited in claim 20, wherein the sixth diffusion contact is substantially equally spaced from each of the fourth linear gate structure and the fifth linear gate structure.