Super-self-aligned contacts and method for making the same
First Claim
1. A semiconductor device, comprising:
- a first linear gate structure;
a second linear gate structure located next to the first linear gate structure, the second linear gate structure separated from the first linear gate structure by a gate pitch, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor;
a third linear gate structure located next to the second linear gate structure, the third linear gate structure separated from the second linear gate structure by the gate pitch, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor;
a fourth linear gate structure located next to the third linear gate structure, the fourth linear gate structure separated from the third linear gate structure by the gate pitch, the fourth linear gate structure forming a third PMOS transistor and a third NMOS transistor;
a fifth linear gate structures located next to the fourth linear gate structure, the fifth linear gate structure separated from the fourth linear gate structure by the gate pitch;
a first gate contact physically connected to the second linear gate structure at a location between the first PMOS transistor and the first NMOS transistor;
a second gate contact physically connected to the third linear gate structure at a location between the second PMOS transistor and the second NMOS transistor; and
a third gate contact physically connected to the fourth linear gate structure at a location between the third PMOS transistor and the third NMOS transistor.
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Accused Products
Abstract
A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.
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Citations
21 Claims
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1. A semiconductor device, comprising:
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a first linear gate structure; a second linear gate structure located next to the first linear gate structure, the second linear gate structure separated from the first linear gate structure by a gate pitch, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor; a third linear gate structure located next to the second linear gate structure, the third linear gate structure separated from the second linear gate structure by the gate pitch, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor; a fourth linear gate structure located next to the third linear gate structure, the fourth linear gate structure separated from the third linear gate structure by the gate pitch, the fourth linear gate structure forming a third PMOS transistor and a third NMOS transistor; a fifth linear gate structures located next to the fourth linear gate structure, the fifth linear gate structure separated from the fourth linear gate structure by the gate pitch; a first gate contact physically connected to the second linear gate structure at a location between the first PMOS transistor and the first NMOS transistor; a second gate contact physically connected to the third linear gate structure at a location between the second PMOS transistor and the second NMOS transistor; and a third gate contact physically connected to the fourth linear gate structure at a location between the third PMOS transistor and the third NMOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification