Memory device comprising electrically floating body transistor

• US 10,461,083 B2
• Filed: 08/21/2018
• Issued: 10/29/2019
• Est. Priority Date: 03/09/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US16/106,643
• Publication Number:
  US 20180358360A1
• Time in Patent Office: 434 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

Claims

1. A semiconductor memory cell comprising:

a memory transistor comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region;

a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions, wherein;

said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region; and

an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region.

2. The semiconductor memory cell of claim 1, further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

3. The semiconductor memory cell of claim 1, wherein said back bias is applied as a constant positive voltage bias.

4. The semiconductor memory cell of claim 1, wherein said back bias is applied as a periodic pulse of positive voltage.

5. The semiconductor memory cell of claim 1, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

6. A semiconductor memory cell comprising:

a memory transistor comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region;

a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions,

wherein said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region,

wherein application of said back bias results in at least two stable floating body charge levels; and

an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region.

7. The semiconductor memory cell of claim 6, further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

8. The semiconductor memory cell of claim 6, wherein said back bias is applied as a constant positive voltage bias.

9. The semiconductor memory cell of claim 6, wherein said back bias is applied as a periodic pulse of positive voltage.

10. The semiconductor memory cell of claim 6, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

11. A semiconductor memory cell comprising:

a memory transistor comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

insulating regions adjacent to said floating body region;

a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions, wherein;

said floating body region is configured to be bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region,

wherein said buried layer region generates impact ionization when said memory cell is in one of said first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states; and

an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region.

12. The semiconductor memory cell of claim 11, further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

13. The semiconductor memory cell of claim 11, wherein said back bias is applied as a constant positive voltage bias.

14. The semiconductor memory cell of claim 11, wherein said back bias is applied as a periodic pulse of positive voltage.

15. The semiconductor memory cell of claim 11, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.