Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 10,461,084 B2
• Filed: 05/10/2019
• Issued: 10/29/2019
• Est. Priority Date: 03/02/2010
• Status: Expired

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/408,649
• Publication Number:
  US 20190267382A1
• Time in Patent Office: 172 Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a floating body region for storing charge indicating a state of said semiconductor memory cell; and

a back-bias region;

wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and

a control circuitry configured to apply said voltage to said back-bias region.

2. The integrated circuit of claim 1, wherein said number of said at least one contact is less than said number of said semiconductor memory cells.

3. The integrated circuit of claim 1, wherein said semiconductor memory cells are connected in series.

4. The integrated circuit of claim 1, wherein said semiconductor memory cells are connected in parallel.

5. The integrated circuit of claim 1, wherein said integrated circuit is fabricated on a bulk silicon substrate.

6. The integrated circuit of claim 1, wherein said number of said at least one contact is two.

7. The integrated circuit of claim 1, wherein said semiconductor memory cells further comprise first and second conductive regions interfacing with said floating body region.

8. The integrated circuit of claim 1, wherein each said semiconductor memory cell further comprises a gate insulated from said floating body region.

9. The integrated circuit of claim 1, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

10. The integrated circuit of claim 9, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.

11. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a floating body region for storing charge; and

a back bias region;

wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and

wherein said at least one control line is connected to a read circuitry; and

a control circuitry configured to apply said voltage to said back-bias region.

12. The integrated circuit of claim 11, wherein said number of said at least one contact is less than said number of said semiconductor memory cells.

13. The integrated circuit of claim 11, wherein said semiconductor memory cells are connected in series.

14. The integrated circuit of claim 11, wherein said semiconductor memory cells are connected in parallel.

15. The integrated circuit of claim 11, wherein said integrated circuit is fabricated on a bulk silicon substrate.

16. The integrated circuit of claim 11, wherein said number of said at least one contact is two.

17. The integrated circuit of claim 11, wherein said semiconductor memory cells further comprise first and second conductive regions interfacing with said floating body region.

18. The integrated circuit of claim 11, wherein each said semiconductor memory cell further comprises a gate insulated from said floating body region.

19. The integrated circuit of claim 11, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

20. The integrated circuit of claim 19, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.