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Cell boundary structure for embedded memory

  • US 10,461,089 B2
  • Filed: 10/23/2018
  • Issued: 10/29/2019
  • Est. Priority Date: 11/29/2016
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) comprising:

  • a semiconductor substrate including a peripheral region and a memory region separated by an isolation structure, wherein the isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material;

    a memory cell on the memory region;

    a dummy control gate structure on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall that faces the peripheral region and that comprises multiple different materials;

    a sidewall spacer on the isolation structure, along the dummy sidewall of the dummy control gate structure, wherein the sidewall spacer has a boundary sidewall that faces the peripheral region and that is smooth; and

    a logic device on the peripheral region.

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