Semiconductor memory device

• US 10,461,093 B2
• Filed: 02/12/2018
• Issued: 10/29/2019
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Minami, Toshifumi, Sato, Atsuhiro, Yonehama, Keisuke, Baba, Yasuyuki, Shinohara, Hiroshi, Kamata, Hideyuki, Higashitsuji, Teppei
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US15/894,832
• Publication Number:
  US 20180175055A1
• Time in Patent Office: 624 Days
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Claims

1. A semiconductor memory device comprising:

a plurality of conducting layers and a plurality of insulating layers that are alternately disposed above a semiconductor substrate;

a plurality of pillars that extend through the alternately-disposed layers of the conductive layers and the insulating layers in a first direction which crosses a surface of the semiconductor substrate, the plurality of pillars being arranged in a second direction along the surface of the semiconductor substrate; and

a plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, extends in the second direction, and is disposed apart from the plurality of pillars in a third direction along the surface of the semiconductor substrate, the third direction being different from the second direction,

wherein the plate has convex portions and non-convex portions alternately arranged on a side of the plate in the second direction, the convex portions and the non-convex portions both extend through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, and the convex portions and at least part of the plurality of pillars are arranged in a staggered manner.

2. The semiconductor memory device according to claim 1, wherein

the convex portions include a first convex portion and a second convex portion adjacent to each other with one of the non-convex portions therebetween, and

a distance between a center of the first convex portion and a center of the second convex portion is substantially equal to a distance between the center of the first convex portion and a center of one of the pillars located between the first and second convex portions in the second direction and adjacent to the first and second convex portions, and substantially equal to a distance between the center of the second convex portion and the center of the one of the pillars.

3. The semiconductor memory device according to claim 1, wherein

the plurality of pillars include a first sub-plurality of pillars arranged adjacent to a first side of the plate and a second sub-plurality of pillars arranged adjacent to a second side of the plate opposite to the first side, and

the first sub-plurality of pillars and the second sub-plurality of pillars are symmetrically arranged with respect to the plate.

4. The semiconductor memory device according to claim 1, further comprising:

a second plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, extends in the second direction, and is disposed apart from the first plate in the third direction, wherein

the second plate has second convex portions and second non-convex portions on a side thereof, and the second convex portions of the second plate and at least part of the plurality of pillars are arranged in a staggered manner.

5. The semiconductor memory device according to claim 4, wherein a group of the plurality of pillars is disposed between the first plate and the second plate and adjacent to the first and second plates with no other pillar therebetween, and the first plate and the second plate are symmetrically arranged with respect to the group of the plurality of pillars.

6. The semiconductor memory device according to claim 4, wherein no plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction and extends in the second direction is disposed between the plate and the second plate.

7. The semiconductor memory device according to claim 1, wherein the convex portions each have a round shape having a first diameter greater than a length of each of the non-convex portions in the second direction.

8. The semiconductor memory device according to claim 1, wherein the convex portions each have a round shape having a first diameter, and the pillars each have a round shape having the second diameter smaller than the first diameter.

9. The semiconductor memory device according to claim 8, further comprising:

an insulating film surrounding each of the pillars, the insulating film having a round shape having the second diameter.

10. The semiconductor memory device according to claim 1, wherein the plate includes a plurality of silicon pillars at positions corresponding to the convex portions, respectively, and an insulating wall surrounding the plurality of silicon pillars.

11. The semiconductor memory device according to claim 1, wherein a bottom of the plate is separate from the semiconductor substrate.

12. The semiconductor memory device according to claim 1, wherein the plurality of pillars each have a length in the first direction longer than a length of the plate in the first direction.

13. A semiconductor memory device comprising:

a plurality of conducting layers and a plurality of insulating layers that are alternately disposed above a semiconductor substrate;

a plurality of pillars that extend through the alternately-disposed layers of the conductive layers and the insulating layers in a first direction which crosses a surface of the semiconductor substrate, the plurality of pillars including a first pillar and a second pillar disposed adjacent to each other in a second direction along the surface of the semiconductor substrate; and

a plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, extends in the second direction, and is disposed apart from the plurality of pillars in a third direction along the surface of the semiconductor substrate, the third direction being different from the second direction,

wherein the plate has convex portions and non-convex portions alternately arranged on a side of the plate in the second direction, the convex portions and the non-convex portions both extend through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, and the convex portions include a first convex portion having a center positioned between a center of the first pillar and a center of the second pillar in the second direction.

14. The semiconductor memory device according to claim 13, wherein the plurality of pillars further includes a third pillar disposed adjacent to the second pillar in the second direction, and the convex portions include a second convex portion having a center positioned between a center of the second pillar and a center of the third pillar in the second direction.

15. The semiconductor memory device according to claim 13, wherein

the plurality of pillars include a first sub-plurality of pillars arranged adjacent to a first side of the plate and a second sub-plurality of pillars arranged adjacent to a second side of the plate opposite to the first side, and

the first sub-plurality of pillars and the second sub-plurality of pillars are symmetrically arranged with respect to the plate.

16. The semiconductor memory device according to claim 13, further comprising:

a second plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, extends in the second direction, and is disposed apart from the first plate in the third direction, wherein

the second plate has convex portions and non-convex portions on a side thereof, and the convex portions of the second plate include a second convex portion having a center positioned between a center of the first pillar and a center of the second pillar in the second direction.

17. The semiconductor memory device according to claim 16, wherein a group of the plurality of pillars is disposed between the first plate and the second plate and adjacent to the first and second plates with no other pillar therebetween, and the first plate and the second plate are symmetrically arranged with respect to the group of the plurality of pillars.

18. The semiconductor memory device according to claim 16, wherein no plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction and extends in the second direction is disposed between the plate and the second plate.

19. The semiconductor memory device according to claim 13, wherein the convex portions each have a round shape having a first diameter, and the pillars each have a round shape having the second diameter smaller than the first diameter.

20. The semiconductor memory device according to claim 19, further comprising:

an insulating film surrounding each of the pillars, the insulating film having a round shape having the second diameter.