Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk

• US 10,461,118 B2
• Filed: 12/15/2017
• Issued: 10/29/2019
• Est. Priority Date: 12/15/2017
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Chen, Yi-Ann, Husain, Abid, Takeuchi, Hideki
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Booker, Vicki B.
• Application Number:
  US15/843,121
• Publication Number:
  US 20190189676A1
• Time in Patent Office: 683 Days
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14647 Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/035236 Superlattices; Multiple quantum well structures
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type
• CPC Class Codes: H01L 31/109 the potential barrier being of the PN heterojunction type

Abstract

A method for making a CMOS image sensor may include forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity types by forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, forming a first well around a periphery of the retrograde well also having the second conductivity type, and forming a second well within the retrograde well having the first conductivity type. Furthermore, first and second superlattices may be respectively formed overlying each of the first and second wells, with each of the first and second superlattices comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A method for making a CMOS image sensor comprising:

forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity type by

forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,

forming a first well around a periphery of the retrograde well also having the second conductivity type,

forming a second well within the retrograde well having the first conductivity type, and

forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The method of claim 1 wherein the first well defines a ring, and wherein the second well is within the ring.

3. The method of claim 1 wherein forming the second well comprises forming a lower portion and an upper portion, the upper portion having a higher dopant concentration than the lower portion.

4. The method of claim 1 further comprising forming a shallow trench isolation (STI) region between the first and second wells.

5. The method of claim 1 further comprising forming a respective shallow trench isolation (STI) region between laterally adjacent photodiodes.

6. The method of claim 1 further comprising forming a respective microlens overlying each of the photodiodes.

7. The method of claim 1 further comprising forming a respective color lens overlying each of the photodiodes.

8. The method of claim 1 wherein the first and second superlattices each further comprises a semiconductor cap layer thereon.

9. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

10. The method of claim 1 wherein the semiconductor monolayers comprise silicon.

11. A method for making a CMOS image sensor comprising:

forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity type by

forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,

forming a first well around a periphery of the retrograde well also having the second conductivity type,

forming a second well within the retrograde well having the first conductivity type, and

forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

forming a respective color lens overlying each of the photodiodes; and

forming a respective microlens overlying each of the color lenses.

12. The method of claim 11 wherein the first well defines a ring, and wherein the second well is within the ring.

13. The method of claim 11 wherein forming the second well comprises forming a lower portion and an upper portion, the upper portion having a higher dopant concentration than the lower portion.

14. The method of claim 11 further comprising forming a shallow trench isolation (STI) region between the first and second wells.

15. A method for making a CMOS image sensor comprising:

forming a plurality of laterally adjacent photodiodes on a semiconductor substrate by

forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,

forming a first well around a periphery of the retrograde well also having the second conductivity type,

forming a second well within the retrograde well having the first conductivity type, and

forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

16. The method of claim 15 wherein the first well defines a ring, and wherein the second well is within the ring.

17. The method of claim 15 wherein forming the second well comprises forming a lower portion and an upper portion, the upper portion having a higher dopant concentration than the lower portion.

18. The method of claim 15 further comprising forming a shallow trench isolation (STI) region between the first and second wells.

19. The method of claim 15 further comprising forming a respective microlens overlying each of the photodiodes.

20. The method of claim 15 further comprising forming a respective color lens overlying each of the photodiodes.