Bottom isolation for nanosheet transistors on bulk substrate

• US 10,461,154 B1
• Filed: 06/21/2018
• Issued: 10/29/2019
• Est. Priority Date: 06/21/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Song, Yi, Liu, Chi-Chun, Bi, Zhenxing, Mochizuki, Shogo
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US16/014,757
• Time in Patent Office: 495 Days
• CPC Class Codes: H01L 21/02601 Nanoparticles fullerenes H10K85/211
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming nanosheets that includes providing a stack of semiconductor material layers on a supporting bulk substrate. A first undercut region filled with a first dielectric material is formed extending from the opening into the bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers. A second undercut region into the bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layer at which the first undercut region is positioned. The first and second dielectric material merged that provide a full isolation region.

Claims

1. A method of forming nanosheets comprising:

providing at least two stacks of semiconductor material layers on a supporting bulk semiconductor substrate, wherein the at least two stacks of semiconductor material layers includes a sacrificial semiconductor layer of a first composition, and a nanosheet semiconductor layer of a second composition, and removing the sacrificial semiconductor layer to provide nanosheets composed of the nanosheet semiconductor layer;

forming a first undercut region filled with a first dielectric material extending from an opening into the supporting bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers; and

forming a second undercut region into the supporting bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layers at which the first undercut region is positioned, wherein the first and second dielectric materials provide an isolation region.

2. The method of claim 1, wherein the first composition is silicon germanium (SiGe), and the second composition is silicon (Si).

3. The method of claim 1, further comprising depositing a supporting dielectric layer over the at least two stacks of semiconductor material layers having said opening into the supporting bulk semiconductor substrate, and exposing a space between adjacent stacks of semiconductor material layer for the at least two stacks of semiconductor material layers prior to forming the first undercut region.

4. The method of claim 3, wherein said forming the first undercut region comprises an isotropic etch introduced through the opening into the supporting bulk semiconductor substrate, the first undercut region extending from the opening into the supporting bulk semiconductor substrate underlying the semiconductor material layers of the stack of semiconductor material layers.

5. The method claim 4, wherein the first dielectric material is deposited using atomic layer deposition (ALD).

6. The method of claim 4, further comprising removing the supporting dielectric layer, and applying an isotropic etch to form the second undercut region into the supporting bulk semiconductor substrate.

7. The method of claim 6, wherein the second dielectric material is blanket deposited by atomic layer deposition (ALD) and etched using an anisotropic etch process.

8. A method of forming a nanosheet device comprising:

providing at least two stacks of semiconductor material layers on a supporting bulk semiconductor substrate;

depositing a supporting dielectric layer over the at least two stacks having an opening exposing a space between adjacent stacks of semiconductor material layer for the at least two stacks of semiconductor material layers;

forming a first undercut region extending from the opening into the supporting bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers;

filling the first undercut region with a first dielectric material;

removing the supporting dielectric layer;

forming a second undercut region into the supporting bulk semiconductor substrate from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layer at which the first undercut region is positioned;

forming a second dielectric material to fill the second undercut region, wherein the first and second dielectric material provide an isolation region underlying an entirety of the semiconductor material layers; and

positioning a channel region of a semiconductor device in a nanosheet provided by at least one of the semiconductor material layers in the stacks of semiconductor material layers.

9. The method of claim 8, wherein the at least two stacks of semiconductor material layers each include a sacrificial semiconductor layer of silicon germanium (SiGe), and a nanosheet semiconductor layer of silicon (Si), the method further including removing the sacrificial semiconductor layer to provide nanosheets composed of the nanosheet semiconductor layer that provide the channel region of the semiconductor device.

10. The method of claim 9, further comprising forming a sacrificial gate structure on a channel region of the at least two stacks of semiconductor material, forming epitaxial source and drain regions on opposing sides of the channel region;

removing the sacrificial semiconductor layer, and replacing the sacrificial gate structure with a functional gate structure.

11. The method of claim 8, wherein said forming the first undercut region comprises an isotropic etch introduced through the opening.

12. The method claim 11, wherein the first dielectric material is deposited using atomic layer deposition (ALD).

13. The method of claim 12, further comprising applying an isotropic etch to form the second undercut region into the supporting bulk semiconductor substrate.

14. The method of claim 13, wherein the second dielectric material is blanket deposited by atomic layer deposition (ALD) and etched using an anisotropic etch process.

15. A semiconductor device comprising:

a bulk semiconductor substrate;

an isolation region present in an upper surface of the bulk semiconductor substrate, the isolation region comprised of two dielectric fill regions having an interface merged within the isolation region, wherein the two fill regions are comprised of a different composition dielectric material;

a plurality of nanosheets present overlying the isolation region, wherein the interface of the two dielectric fill regions is substantially merged under the width of the plurality of nanosheets;

a gate structure present on a channel region portion of the plurality of nanosheets; and

source and drain regions on opposing sides of the channel region portion of the plurality of nanosheets.

16. The semiconductor device of claim 15, wherein an entirety of the plurality of nanosheets is separated from the bulk semiconductor substrate by the isolation region.