GaN device with floating field plates

• US 10,461,161 B1
• Filed: 01/23/2018
• Issued: 10/29/2019
• Est. Priority Date: 01/23/2017
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin
• Primary Examiner(s): Moore, Whitney
• Application Number:
  US15/878,309
• Time in Patent Office: 644 Days
• Field of Search: None
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A lateral transistor includes a source a gate and a drain connection to a transition layer within a semiconductor substrate. One or more capacitively coupled floating field plates are connected to the source connection such that the source voltage is uniformly distributed across the field plates.

Claims

1. A semiconductor device comprising:

a substrate including a transition layer that can form a two-dimensional electron gas;

a source electrode ohmically coupled to the transition layer;

a drain electrode ohmically coupled to the transition layer;

a gate stack formed on the transition layer; and

a field termination structure spaced apart from the transition layer and positioned between the gate stack and the drain electrode, wherein the field termination structure includes a source plate electrically connected to the source electrode and at least one capacitively coupled floating plate.

2. The semiconductor device of claim 1 wherein the field termination structure is disposed within a single layer and there are a plurality of floating plates capacitively coupled by adjacent edges to one another.

3. The semiconductor device of claim 1 wherein the field termination structure is formed on a metal layer that includes a drain plate coupled to the drain electrode, a source plate coupled to the source electrode and the at least one floating plate.

4. The semiconductor device of claim 3 wherein the at least one floating plate includes a plurality of isolated separate floating plates that are uniformly spaced apart from one another and are positioned between the drain plate and the source plate.

5. The semiconductor device of claim 4 wherein a voltage potential applied between the source electrode and the drain electrode is evenly distributed across the plurality of separate floating plates.

6. The semiconductor device of claim 1 wherein the field termination structure includes a first field plate formed on a first metal layer and a second field plate formed on a second metal layer that is spaced apart from the first metal layer.

7. The semiconductor device of claim 6 wherein the first field plate includes a plurality of separate floating plates that are uniformly spaced apart from one another and the second field plate includes a plurality of separate floating upper metal plates that are uniformly spaced apart from one another.

8. The semiconductor device of claim 7 wherein the plurality of separate floating plates are laterally positioned such that each of the plurality of separate floating upper metal plates overlaps at least two floating plates.

9. The semiconductor device of claim 6 wherein the substrate comprises gallium nitride.

10. A transistor comprising:

a substrate comprising a semiconductor material;

a source electrode coupled to the substrate;

a drain electrode coupled to the substrate;

a gate stack formed on the substrate; and

a field termination structure positioned between the gate stack and the drain electrode, wherein the field termination structure includes a source plate electrically connected to the source electrode and at least one capacitively coupled isolated plate.

11. The transistor of claim 10 wherein the substrate comprises a transition layer capable of forming a two-dimensional electron gas.

12. The transistor of claim 10 wherein the field termination structure is formed within a single layer and there are a plurality of isolated plates capacitively coupled by adjacent edges to one another.

13. The transistor of claim 10 wherein the field termination structure is formed on a gate metal layer that includes a drain plate coupled to the drain electrode, a source plate coupled to the source electrode and the at least one isolated plate positioned between the drain plate and the source plate.

14. The transistor of claim 13 wherein the at least one isolated plate includes a plurality of separate isolated plates that are uniformly spaced apart from one another and are positioned between the drain plate and the source plate.

15. The transistor of claim 10 wherein the field termination structure includes a first field plate formed on a gate metal layer and a second field plate formed on an upper metal layer that is spaced apart from the gate metal layer.

16. The transistor of claim 15 wherein the first field plate includes a plurality of separate floating plates that are uniformly spaced apart from one another and the second field plate includes a plurality of isolated upper metal plates that are uniformly spaced apart from one another.

17. The transistor of claim 16 wherein the plurality of isolated floating plates are laterally positioned such that each of the plurality of separate floating upper metal plates overlaps at least two floating plates.

18. A semiconductor device comprising:

a substrate including a semiconducting layer;

an ohmic metal layer formed on the substrate and including a source portion and a drain portion;

a gate stack formed on the substrate;

a metal layer formed above and separated from the ohmic metal layer and including a source plate, a drain plate and a plurality of electrically isolated plates; and

a top metal layer formed above and separated from the metal layer and including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal is electrically connected to the gate stack, the source terminal is electrically connected to the source plate, and the drain terminal is electrically connected to the drain plate.

19. The semiconductor device of claim 18 wherein the plurality of electrically isolated plates are capacitively coupled by adjacent edges to one another.

20. The semiconductor device of claim 18 wherein the plurality of electrically isolated plates are positioned between the source plate and the drain plate.