Three-dimensional memory device with thickened word lines in terrace region and method of making thereof

• US 10,461,163 B2
• Filed: 11/15/2017
• Issued: 10/29/2019
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Kanakamedala, Senaka Krishna, Kanno, Yoshihiro, Makala, Raghuveer S., Zhang, Yanli, Liu, Jin, Chowdhury, Murshed, Lee, Yao-Sheng
• Primary Examiner(s): Dulka, John P.
• Application Number:
  US15/813,579
• Publication Number:
  US 20190148506A1
• Time in Patent Office: 713 Days
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers has a respective first thickness in a memory array region and a respective second thickness that is greater than the respective first thickness in a stepped terrace region;

memory stack structures located in the memory array region and vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and

contact via structures located in the terrace region and contacting a respective one of the electrically conductive layers.

2. The three-dimensional memory device of claim 1, wherein:

each of the electrically conductive layers includes a contact portion located in the terrace region; and

each of the contact via structures contacts the contact portion of a respective one of the electrically conductive layers.

3. The three-dimensional memory device of claim 2, wherein:

each of the electrically conductive layers has the respective first thickness in the terrace region between the contact portion and the memory array region; and

each of the electrically conductive layers has the respective second thickness in the contact portion.

4. The three-dimensional memory device of claim 3, wherein:

each of the electrically conductive layers other than the topmost one of the electrically conductive layers has the respective first thickness in a portion of the terrace region having an areal overlap with at least one overlying electrically conductive layer in a plan view; and

each of the contact portions of the electrically conductive layers other than the topmost one of the electrically conductive layers does not have an areal overlap with any overlying electrically conductive layers in the plan view.

5. The three-dimensional memory device of claim 2, wherein each of the electrically conductive layers consists essentially of the same one or more metallic materials in the contact portion and in the memory array region.

6. The three-dimensional memory device of claim 2, wherein each of the electrically conductive layers comprises a first metallic material having the respective first thickness in the contact portion and in the memory array region.

7. The three-dimensional memory device of claim 6, wherein each of the electrically conductive layers further comprises a second metallic material located over the first metallic material in each of the contact portions, and wherein the second metallic material is absent in the memory array region.

8. The three-dimensional memory device of claim 7, wherein the first metallic material comprises tungsten and the second metallic material comprises ruthenium.

9. The three-dimensional memory device of claim 1, further comprising:

a retro-stepped dielectric material portion located in the terrace region and overlying the alternating stack and including a stepped bottom surface that contacts surfaces of the electrically conductive layers; and

dielectric spacers located on sidewalls of a respective one of the insulating layers, extending upward to a level of one of the electrically conductive layers that overlies the respective one of the insulating layers, and contacting the retro-stepped dielectric material portion, wherein the insulating layers are laterally spaced from the retro-stepped dielectric material portion by the dielectric spacers.

10. The three-dimensional memory device of claim 9, wherein each of the electrically conductive layers includes a laterally extending portion adjoined to the contact portion and having a lesser thickness than the respective first thickness and overlying a respective one of the dielectric spacers.

11. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers includes a peripheral portion that contacts a sidewall of an underlying one of the insulating layers.

12. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers comprises:

a first metallic material portion having the respective first thickness; and

a second metallic material portion located inside the contact portion, wherein a difference between the respective second thickness and the respective first thickness for each of the electrically conductive layers equals to a thickness of a horizontal portion of the second metallic material portion.

13. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the contact via structures comprise word line contact via structures;

the electrically conductive layers comprise word lines of the three dimensional memory device; and

the contact via structures electrically connect each word line to a respective peripheral device of a driver circuit located below the alternating stack.

14. A method of forming a three-dimensional memory device, comprising:

forming an alternating stack of insulating layers and sacrificial material layers over a substrate, wherein the alternating stack includes a memory array region in which each of the sacrificial material layers is present and a terrace region in which the sacrificial material layers have a respective lateral extent that decreases as a function of a vertical distance from the substrate;

forming self-aligned material portions on physically exposed surfaces of the sacrificial material layers in the terrace region employing a selective deposition process in which a material selectively grows from the physically exposed surfaces of the sacrificial material layers;

forming memory stack structures through the alternating stack in the memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;

replacing at least the sacrificial material layers with conductive material layers; and

forming contact via structures that contact a respective one of the conductive material layers.

15. The method of claim 14, wherein:

the self-aligned material portions comprise sacrificial material portions; and

the method further comprises replacing the sacrificial material portions with portions of the conductive material layers.

16. The method of claim 15, wherein:

the sacrificial material layers comprise silicon nitride;

the insulating layers comprise silicon oxide; and

the selective deposition process deposits self-aligned silicon nitride portions from silicon nitride surfaces of the sacrificial material layers without growing silicon nitride from silicon oxide surfaces of the insulating layers employing an incubation time difference for silicon nitride between the silicon nitride surfaces and the silicon oxide surfaces.

17. The method of claim 14, wherein:

the self-aligned material portions comprise metallic material portions; and

the conductive material layers are formed on surfaces of the metallic material portions.

18. The method of claim 17, wherein the metallic material portions comprise ruthenium.

19. The method of claim 14, further comprising:

forming dielectric spacers on sidewalls of vertically neighboring pairs of an insulating layer and an overlying sacrificial material layer in the terrace region prior to forming the self-aligned material portions; and

forming a retro-stepped dielectric material portion over the alternating stack and the dielectric spacers in the terrace region after forming the self-aligned material portions.

20. The method of claim 19, wherein:

the self-aligned material portions are selectively deposited on exposed portions of top surfaces of the sacrificial material layers in the terrace region and are not deposited on sidewalls of the dielectric spacers;

the retro-stepped dielectric material portion is formed on sidewalls of the dielectric spacers; and

each of the insulating layers and the sacrificial material layers is laterally spaced from the retro-stepped dielectric material portion by a respective one of the dielectric spacers.

21. The method of claim 14, wherein the self-aligned material portions grow from a top surface and a sidewall surface of each of the sacrificial material portions.