Semiconductor device

• US 10,461,180 B2
• Filed: 06/21/2018
• Issued: 10/29/2019
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Naito, Tatsuya
• Primary Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US16/015,149
• Publication Number:
  US 20190027591A1
• Time in Patent Office: 495 Days
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/0761 Vertical bipolar transistor in combination with diodes only
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.

Claims

1. A semiconductor device comprising:

a first conductivity type drift region formed on a semiconductor substrate;

a gate trench portion provided reaching from an upper surface of the semiconductor substrate to an inner part of the semiconductor substrate and provided extending in a predetermined extending direction from the upper surface;

a first mesa portion being in direct contact with one of two side walls of the gate trench portion;

a second mesa portion being in direct contact with an opposite side of the one of two side walls of the gate trench portion;

a first conductivity type accumulation region having doping concentration higher than that in the drift region, which is provided being in direct contact with the gate trench portion above the drift region;

a second conductivity type base region provided being in direct contact with the gate trench portion above the accumulation region;

a first conductivity type emitter region having doping concentration higher than that in the drift region, which is provided on the upper surface of the semiconductor substrate such that it is in direct contact with the one of two side walls of the gate trench portion in at least the first mesa portion; and

an electrically floating second conductivity type floating region provided below the base region in the second mesa portion and at a position shallower than a bottom of the gate trench portion.

2. The semiconductor device according to claim 1, wherein a width of the second mesa portion in an array direction perpendicular to the extending direction is larger than a width of the first mesa portion in the array direction.

3. The semiconductor device according to claim 2, wherein a plurality of the floating regions are provided in the array direction.

4. The semiconductor device according to claim 3, wherein the plurality of the floating regions are provided at a same interval as the width of the first mesa portion in the array direction.

5. The semiconductor device according to claim 2, wherein a width of the floating region in the array direction is equal to a width of the gate trench portion in the array direction of the gate trench portion.

6. The semiconductor device according to claim 2, wherein

a sum of the width of the first mesa portion and the width of the gate trench portion in the array direction is equal to a sum of an interval between one floating region among a plurality of the floating regions and another one of the plurality of floating regions adjacent to the one floating region in the array direction, and the width of the one floating region in the array direction.

7. The semiconductor device according to claim 2, wherein among a plurality of the floating regions, a width of a floating region positioned on a center side of the second mesa portion in the array direction is larger than a width of a floating region closest to the gate trench portion in the array direction.

8. The semiconductor device according to claim 1, wherein the floating region is provided below the accumulation region in a depth direction of the semiconductor substrate.

9. The semiconductor device according to claim 1, wherein the floating region is provided at a depth between 2.6 μ

m and 4.8 μ

m inclusive from the upper surface of the semiconductor substrate in a depth direction of the semiconductor substrate.

10. The semiconductor device according to claim 1, wherein the floating region is provided such that a depth from a lower surface of the floating region to a bottom of the gate trench portion is less than or equal to 1.9 μ

m in a depth direction of the semiconductor substrate.

11. A semiconductor device comprising:

a first conductivity type drift region formed on a semiconductor substrate;

a gate trench portion provided reaching from an upper surface of the semiconductor substrate to an inner part of the semiconductor substrate and provided extending in a predetermined extending direction from the upper surface;

a first mesa portion being in direct contact with one of two side walls of the gate trench portion;

a second mesa portion being in direct contact with an opposite side of the one of two side walls of the gate trench portion;

a first conductivity type accumulation region having doping concentration higher than that in the drift region, which is provided being in direct contact with the gate trench portion above the drift region;

a second conductivity type base region provided being in direct contact with the gate trench portion above the accumulation region;

a first conductivity type emitter region having doping concentration higher than that in the drift region, which is provided on the upper surface of the semiconductor substrate such that it is in direct contact with the one of two side walls of the gate trench portion in at least the first mesa portion;

an electrically floating second conductivity type floating region provided below the base region in the second mesa portion and spaced from the gate trench portion; and

a first conductivity type emitter region having doping concentration higher than that in the drift region, which is provided on the upper surface of the semiconductor substrate in the second mesa portion, such that it is in direct contact with the other of the two side walls of the gate trench portion, wherein

the floating region does not exist in at least a part below the emitter region provided in the second mesa portion, in a depth direction of the semiconductor substrate.

12. A semiconductor device comprising:

a first conductivity type drift region formed on a semiconductor substrate;

a gate trench portion provided reaching from an upper surface of the semiconductor substrate to an inner part of the semiconductor substrate and provided extending in a predetermined extending direction from the upper surface;

a first mesa portion being in direct contact with one of two side walls of the gate trench portion;

a second mesa portion being in direct contact with an opposite side of the one of two side walls of the gate trench portion;

a first conductivity type accumulation region having doping concentration higher than that in the drift region, which is provided being in direct contact with the gate trench portion above the drift region;

a second conductivity type base region provided being in direct contact with the gate trench portion above the accumulation region;

a first conductivity type emitter region having doping concentration higher than that in the drift region, which is provided on the upper surface of the semiconductor substrate such that it is in direct contact with the one of two side walls of the gate trench portion in at least the first mesa portion;

an electrically floating second conductivity type floating region provided below the base region in the second mesa portion and spaced from the gate trench portion; and

an interlayer dielectric film formed on the semiconductor substrate, wherein

the interlayer dielectric film has a contact hole, and

the floating region does not exist below the contact hole in the second mesa portion in a depth direction of the semiconductor substrate.