Assemblies having conductive structures along pillars of semiconductor material

• US 10,461,185 B2
• Filed: 05/10/2018
• Issued: 10/29/2019
• Est. Priority Date: 12/22/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Li, Hong, Poelstra, Erica L.
• Primary Examiner(s): Li, Meiya
• Application Number:
  US15/976,720
• Publication Number:
  US 20190198668A1
• Time in Patent Office: 537 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 23/49 wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 : DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/488 : Word lines
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type

Abstract

Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

Claims

1. An assembly, comprising:

pillars of semiconductor material over a base, the pillars of semiconductor material being arranged in rows that extend along a first direction;

the rows further comprising an intervening spacing regions between the pillars of semiconductor material such that the intervening spacing regions alternate with the silicon pillars within each of the rows,

the pillars of semiconductor material having top surfaces at a first maximum height above the base, and the intervening spacing regions comprising spacing structures having top surfaces at a second maximum height above the base, the second maximum height being below the first maximum height;

the rows being spaced from each other by gap regions;

conductive structures within the gap regions between the rows, the conductive structures each extending along the first direction along a plurality of the pillars of semiconductive material, two of the conductive structures being within each of the gap regions and being spaced apart from one another by a separating region, the separating region having a bottom surface that undulates across semiconductor segments and insulative segments, a height of each of the semiconductor segments being higher than that of each of the insulative segments relative to the base;

channel regions within the pillars of semiconductor material;

gates within the conductive structures; and

transistors, with each of the transistors comprising one of the channel regions and at least one of the gates.

2. The assembly of claim 1, wherein the semiconductor segments and the insulative segments alternate with one another along the first direction.

3. The assembly of claim 1, wherein the spacing structures are insulative.

4. The assembly of claim 1, wherein the spacing structures are conductive.

5. The assembly of claim 1, wherein the conductive structures are comprised by wordlines;

and the assembly further comprising;

digit lines under the pillars of semiconductor material and extending along a second direction which intersects the first direction;

memory cells coupled with the transistors, with each of the memory cells being uniquely addressed by one of the wordlines in combination with one of the digit lines.