Integrated circuit devices and methods of manufacturing the same

• US 10,461,187 B2
• Filed: 06/08/2018
• Issued: 10/29/2019
• Est. Priority Date: 05/26/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cantoro, Mirco, Heo, Yeon-cheol, Toledano Luque, Maria
• Primary Examiner(s): Wright, Tucker J
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US16/003,959
• Publication Number:
  US 20180294353A1
• Time in Patent Office: 508 Days
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

Claims

1. An integrated circuit device comprising:

a substrate comprising a main surface;

a transistor (TR) comprising a first section, a vertical channel region, and a second section on the main surface; and

a gate electrode on the vertical channel region,

wherein the first section, the vertical channel region, and the second section extend from the main surface in a first direction perpendicular to the main surface, wherein the vertical channel region and the first and second sections have the same composition as each other and have different crystal phases from each other, and wherein the vertical channel region has a first width in a second direction parallel to the main surface and the first section has a second width in the second direction, the first width being narrower than the second width.

2. The integrated circuit device of claim 1, wherein the second section constitutes a drain region.

3. The integrated circuit device of claim 2, wherein a source region is between the vertical channel region and the substrate.

4. The integrated circuit device of claim 1, further comprising a gate dielectric layer between the gate electrode and the vertical channel region.

5. The integrated circuit device of claim 1, wherein the substrate comprises a Group IV material or a Group III-V material, and the main surface has a {111} crystal plane.

6. The integrated circuit device of claim 1, wherein the first section, the vertical channel region, and the second section comprise a Group III-V material.

7. The integrated circuit device of claim 1, wherein the first section, the vertical channel region, and the second section comprise at least one Group III element selected from indium (In), gallium (Ga), and aluminum (Al) and at least one Group V element selected from arsenic (As), phosphorus (P), and antimony (Sb), and

the first section and the vertical channel region have the different crystal phases respectively selected from a zinc-blende (ZB) crystal phase and a wurtzite (WZ) crystal phase.

8. The integrated circuit device of claim 1, wherein the gate electrode has an annular shape surrounding the vertical channel region.

9. An integrated circuit device comprising:

a substrate comprising a main surface;

a transistor (TR) comprising a first section, a vertical channel region, and a second section on the main surface, wherein the first section, the vertical channel region, and the second section extend from the main surface in a first direction perpendicular to the main surface, wherein the vertical channel region and the first and second sections have the same composition as each other and have different crystal phases from each other;

a gate electrode on the vertical channel region; and

an interfacial layer between the vertical channel region and the gate electrode, the vertical channel region being recessed relative to the first and second sections in a second direction parallel to the main surface.

10. The integrated circuit device of claim 9, wherein the interfacial layer comprises III-V compound.

11. The integrated circuit device of claim 9, wherein the interfacial layer is in a recessed region of the vertical channel region.

12. The integrated circuit device of claim 11, wherein the gate electrode is in the recessed region of the vertical channel region.

13. The integrated circuit device of claim 9, wherein the second section constitutes a drain region.

14. The integrated circuit device of claim 13, wherein a source region is between the vertical channel region and the substrate.

15. The integrated circuit device of claim 9, wherein the substrate comprises a Group IV material or a Group III-V material, and the main surface has a {111} crystal plane.

16. The integrated circuit device of claim 9, wherein the first section, the vertical channel region, and the second section comprise a Group III-V material.

17. The integrated circuit device of claim 9, wherein the first section, the vertical channel region, and the second section comprise at least one Group III element selected from indium (In), gallium (Ga), and aluminum (Al) and at least one Group V element selected from arsenic (As), phosphorus (P), and antimony (Sb), and the first section and the vertical channel region have the different crystal phases respectively selected from a zinc-blende (ZB) crystal phase and a wurtzite (WZ) crystal phase.

18. The integrated circuit device of claim 9, wherein the gate electrode has an annular shape surrounding the vertical channel region.