Thin film transistor and manufacturing method thereof

• US 10,461,199 B2
• Filed: 03/05/2018
• Issued: 10/29/2019
• Est. Priority Date: 12/28/2017
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Inventors: Xia, Hui, Tan, Zhiwei, Chen, Shu Jhih
• Primary Examiner(s): Woldegeorgis, Ermias T
• Application Number:
  US15/911,555
• Publication Number:
  US 20190207030A1
• Time in Patent Office: 603 Days
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present disclosure discloses a manufacturing method of a thin film transistor, including: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer and the substrate; forming an active layer on the gate insulating layer; and simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method. In the present disclosure, the chemical plating method is combined with the lift-off method, so that the wet-etching method is not used for forming the source and the drain, and thus the IGZO at the channel is not required to be protected by the etching-stop-layer. Therefore, while simplifying the production process, but also can reduce costs.

Claims

1. A thin film transistor manufacturing method, comprising:

forming a gate layer on a substrate;

forming a gate insulating layer on the gate layer and the substrate;

forming an active layer on the gate insulating layer; and

simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method;

wherein the simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method comprises;

coating a photoresist layer on the gate insulating layer and the active layer;

patterning the photoresist layer to remove a photoresist layer at a position where the source and the drain are to be formed to expose the active layer;

doping the exposed portion of the active layer to form a first conductor portion and a second conductor portion; and

disposing the source on the first conductor portion, and disposing the drain on the second conductor portion;

using a chemical plating method to form a metal film layer on a remaining photoresist layer and an exposed portion of the active layer; and

stripping the remaining photoresist layer with a stripping liquid to peel off the metal film layer on the remaining photoresist layer to form the source and the drain.

2. The thin film transistor manufacturing method according to claim 1, wherein the source comprises a first bottom surface in contact with the first conductor portion, a first top surface opposite to the first bottom surface, and a first side surface connected between the first bottom surface and the first top surface, an included angle between the first side surface and the first bottom surface is less than or equal to 65°

.

3. The thin film transistor manufacturing method according to claim 2, wherein the drain comprises a second bottom surface in contact with the second conductor portion, a second top surface opposite to the second bottom surface, and a second side surface connected between the second bottom surface and the second top surface, an included angle between the second side surface and the second bottom surface is less than or equal to 65°

.

4. The thin film transistor manufacturing method according to claim 1, wherein the drain comprises a second bottom surface in contact with the second conductor portion, a second top surface opposite to the second bottom surface, and a second side surface connected between the second bottom surface and the second top surface, an included angle between the second side surface and the second bottom surface is less than or equal to 65°

.