Solar cell and method for producing same

• US 10,461,208 B2
• Filed: 05/30/2017
• Issued: 10/29/2019
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: Rec Solar Pte. Ltd. (Reliance New Energy Ltd.)
• Original Assignee: Rec Solar Pte. Ltd. (Reliance New Energy Ltd.)
• Inventors: Kirkengen, Martin, Sauar, Erik
• Primary Examiner(s): Malek, Maliheh
• Application Number:
  US15/608,310
• Publication Number:
  US 20170317224A1
• Time in Patent Office: 882 Days
• CPC Class Codes: H01L 31/022441 Electrode arrangements specially adapted for back-contact solar cells
• CPC Class Codes: H01L 31/074 comprising a heterojunction with an element of Group IV of the Periodic Table, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
• CPC Class Codes: H01L 31/0747 comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
• CPC Class Codes: H01L 31/075 the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A rear contact heterojunction solar cell and a fabricating method. The solar cell comprises a silicon substrate having a passivating layer and an intrinsic amorphous silicon layer. At a back side of the intrinsic amorphous silicon layer, an emitter layer and a base layer are provided. Interposed between these emitter and base layers is a separation layer comprising an electrically insulating material. This separation layer as well as the base layer and emitter layer may be generated by vapor deposition. Due to such processing, adjacent regions of the emitter layer and the separating layer and adjacent regions of the base layer and the separating layer partially laterally overlap in overlapping areas in such a way that at least a part of the separating layer is located closer to the substrate than an overlapping portion of the respective one of the emitter layer and the base layer.

Claims

1. A method for fabricating a rear contacted heterojunction intrinsic thin layer solar cell wherein the rear side is formed by at least:

providing a silicon substrate with a front surface and a rear surface;

depositing a continuous thin layer of intrinsic amorphous silicon over the entire rear surface of the silicon substrate, the intrinsic amorphous silicon layer having a front surface adjacent to the rear surface of the silicon substrate and the intrinsic amorphous silicon layer having a back surface opposite to the front surface of the intrinsic amorphous silicon layer;

depositing a separation layer comprising an electrically insulating material wherein the separation layer is deposited through a mask such that it covers separation portions of the back surface of the intrinsic amorphous silicon layer;

depositing an emitter layer comprising a doped semiconducting material of a first doping polarity wherein the emitter layer is deposited through a mask such that it covers an emitter portion of the back surface of the intrinsic amorphous silicon layer adjacent to the separation portions;

depositing a base layer comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and with higher doping concentration than the silicon substrate wherein the base layer is deposited though a mask such that it covers a base portion of the back surface of the intrinsic amorphous silicon layer adjacent to the separation portions.

2. The method of claim 1, wherein the mask used for depositing at least one of the separation layer, the base layer and the emitter layer has tilted edges, narrowest at the bottom.

3. The method of claim 1, wherein openings in a mask used for depositing the separation layer when positioned for depositing the separation layer partially laterally overlap openings in a mask used for depositing one of the base layer and the emitter layer when positioned for depositing the respective layer.

4. The method of claim 1, wherein, when an alignment process of the masks used for depositing the separation layer, the emitter layer and the base layer is technically limited to a minimum alignment precision, the width and spacing of openings in the masks for depositing the separation regions each have a width and spacing of at least twice minimum alignment precision.

5. The method of claim 1, wherein the same mask is used for various depositions of the separation layer deposition, the base layer deposition and the emitter layer deposition, and wherein different mask alignments are all just relative to the alignment of a first patterned layer deposition.

6. The method of claim 1, wherein the mask for depositing the separation layer contains a plurality of bridges allowing layer deposition under the bridge while the bridges support a mechanical stability of the mask.

7. The method of claim 1, where the mask is made of a material with a coefficient of thermal expansion same or close to that of the silicon substrate.

8. The method of claim 1, wherein a normal originating from an outside facing surface of the separation layer has a direction component facing away from the rear intrinsic amorphous silicon layer for all locations of the surface of the separation layer not being in contact with the intrinsic amorphous silicon layer.

9. The method of claim 1, wherein at least a part of the separation layer forms a continuous phase with the intrinsic amorphous silicon layer and wherein a cross section of the solar cell shows that the intrinsic amorphous silicon layer is thinnest under a middle of electrodes contacting one of the emitter layer and the base layer and is at least 20% thicker towards at least one of electrode edges and in the majority of the separation layer.

10. The method of claim 1, wherein the separation layer comprises at least one layer of a dielectric material with good passivating and electrical insulation properties.

11. The method of claim 1, wherein the separation layer consists of one layer of intrinsic amorphous silicon with good passivating properties and at least one layer of dielectric with good optical reflection and electrical insulation properties, and wherein a tail portion of the intrinsic amorphous silicon of the separation layer extends under and laterally overlaps with one of the adjacent base layer or emitter layer.

12. The method of claim 1, where the substrate is a silicon wafer cut in the <

111>

crystal orientation and being polished at the rear surface.

13. The method of claim 1, wherein the rear surface of the silicon substrate has a texture.

14. The method of claim 1, wherein the separation layer comprises a first portion that is arranged between the silicon substrate and the base layer and a second portion that is arranged between the silicon substrate and the emitter layer.