Vertical structure LEDs

• US 10,461,217 B2
• Filed: 02/05/2019
• Issued: 10/29/2019
• Est. Priority Date: 04/09/2002
• Status: Expired due to Fees

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Innotek Company Limited (LG Corporation)
• Inventors: Lee, Jong Lam, Jeong, In-Kwon, Yoo, Myung Cheol
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US16/268,161
• Publication Number:
  US 20190172974A1
• Time in Patent Office: 266 Days
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01C 7/008 Thermistors H01C7/02 - H01C7/06 take precedence
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10S 438/958 Passivation layer
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method for manufacturing a light emitting diode can include forming a GaN-based semiconductor structure with a thickness of less than 5 microns on a substrate, the GaN-based semiconductor structure having a p-type GaN-based semiconductor layer; an active layer on the p-type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode having multiple metal layers on the GaN-based semiconductor structure; forming a metal support layer on the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode on a flat portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure, not only with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure but also with contacting the flat portion; and forming an insulating layer on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, in which a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure and a side surface of the n-type electrode, and a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

Claims

1. A method for manufacturing a light emitting diode, comprising:

forming a GaN-based semiconductor structure with a thickness of less than 5 microns on a substrate, the GaN-based semiconductor structure comprising;

a p-type GaN-based semiconductor layer;

an active layer on the p-type GaN-based semiconductor layer; and

an n-type GaN-based semiconductor layer on the active layer;

forming a p-type electrode having multiple metal layers on the GaN-based semiconductor structure;

forming a metal support layer on the p-type electrode;

removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure;

forming an n-type electrode on a flat portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure, not only with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure but also with contacting the flat portion; and

forming an insulating layer on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure,

wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure and a side surface of the n-type electrode, and

wherein a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

2. The method according to claim 1, further comprising:

forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and

forming a metal pad layer at the open space, the metal pad layer comprising;

a first portion having a flat bottom surface on the n-type electrode; and

a second portion having stepped surfaces.

3. The method according to claim 2 wherein a width of the open space is different from a width of the metal pad layer, and

wherein a width of the p-type electrode is wider than a width of the n-type electrode.

4. The method according to claim 1, wherein the insulating layer includes at least one of SiO₂ or Si₃N₄, and

wherein the insulating layer is formed to extend to between the p-type GaN-based semiconductor layer of the GaN-based semiconductor structure and the metal support layer, with overlapping the first part of the insulating layer in the thickness direction of the GaN-based semiconductor structure.

5. The method according to claim 1, wherein a thickness of the GaN-based semiconductor structure is smaller than a thickness of the metal support layer.

6. The method according to claim 1, wherein the metal support layer is made of least two metals selected from. the group consisting of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, and W.

7. The method according to claim 2, wherein the first part of the insulating layer contacts an upper surface of the n-electrode, and

wherein an uppermost surface of the metal pad layer is formed at a higher position than the first part of the insulating layer.

8. The method according to claim 1, wherein a ratio of the thickness occupied by the p-type GaN-based semiconductor layer in the GaN-based semiconductor structure is higher than 1%.

9. The method according claim 1, wherein an area of a portion contacting the p-type GaN-based semiconductor layer in the insulating layer is smaller than an area of a portion contacting the n-type GaN-based semiconductor layer in the insulating layer.

10. The method according to claim 1, wherein the p-type electrode includes Pt or Ni.

11. The method according to claim 2, wherein the metal ad layer includes at least one of Cr or Au.

12. A method for manufacturing a light emitting diode, comprising:

forming a GaN-based semiconductor structure with a thickness of less than 5 μ

m on a substrate, the GaN-based semiconductor layer comprising;

a p-type GaN-based semiconductor layer;

an active layer on the p--type GaN-based semiconductor layer; and

an n-type GaN-based semiconductor layer on the active layer;

forming a p-type electrode on the p-type GaN-based semiconductor layer;

forming a metal support layer on the p-type electrode;

removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure;

forming an n-type electrode on the upper surface of the GaN-based semiconductor structure, with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure and with contacting a flat top portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure;

forming an insulating layer on an upper surface of the GaN-based semiconductor structure and on a side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure, a side surface of the n-type electrode, and a top surface of the n-type electrode;

forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and

forming a metal pad layer at the open space, the metal pad layer comprising;

a first portion having a flat bottom surface on the n-type electrode; and

a second portion having stepped surfaces, the first width of the first portion of the metal pad layer being different from a second width of the second portion of the metal pad layer,

wherein an area of a portion contacting the p-type GaN-based semiconductor layer in the insulating layer is smaller than an area of a portion contacting the n-type GaN-based semiconductor layer in the insulating layer,

wherein the p-type electrode contacts a top surface of the metal support layer and a bottom surface of the GaN-based semiconductor structure, and

wherein the second portion of the metal pad layer overlaps the first portion of the metal pad layer in the thickness direction of the GaN-based semiconductor structure.

13. The method according to claim 12, wherein a sum of the thickness of the GaN-based semiconductor structure and a thickness of the p-type electrode is less than a sum of 10 nm and 5 μ

m.

14. The method according to claim 12, wherein the metal pad layer is formed to have a thickness greater than a thickness of the n-type electrode.

15. The method according to claim 12, wherein the GaN-based semiconductor structure is formed to have a width different from a width of the p-type electrode.

16. The method according to claim 12, wherein the p-type electrode is formed to have a width larger than a width of the n-type electrode.

17. The method according to claim 12, wherein the p-type electrode is formed to have a width smaller than a width of the metal support layer.

18. The method according to claim 12, wherein the n-type electrode comprises at least one of Al or Ti and the p-type electrode comprises at least one layer of Pt or Ni.

19. The method according to claim 12, wherein the insulating layer is formed to extend to between the p-type GaN-based semiconductor layer of the GaN-based semiconductor structure and the metal support layer, and

wherein the extended part of the insulating layer overlaps the first part of the insulating layer in the thickness direction of the GaN-based semiconductor structure.

20. A method for manufacturing a light emitting diode, comprising:

forming a GaN-based semiconductor structure with a thickness of a less than 5 microns on a substrate, the GaN-based semiconductor layer comprising;

a p-type GaN-based semiconductor layer;

an active layer on the p-type GaN-based semiconductor layer; and

an n-type GaN-based semiconductor layer on the active layer;

forming a p-type electrode having multiple metal layers on the p-type GaN-based semiconductor layer with contacting a bottom surface of the Gall-based semiconductor structure;

forming a metal support layer comprising Ti and non-metal material on the p-type electrode, a top surface of the metal support layer contacting the p-type electrode;

removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure;

forming an n-type electrode comprising Ti and Al on the upper surface of the GaN-based semiconductor structure, with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure;

forming an insulating layer including at least one of SiO₂ or Si₃N₄, on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure;

forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and

forming a metal pad layer at the open space, an uppermost surface of the metal pad layer being formed at a higher position than the first part of the insulating layer,

wherein a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.