Wafer level package with integrated or embedded antenna
First Claim
Patent Images
1. Wafer level package with integrated antenna, comprising:
- a contacting layer;
a redistribution layer with the integrated antenna;
a chip layer comprising at least one chip arranged between the contacting layer and the redistribution layer;
wherein the integrated antenna is laterally arranged in the redistribution layer such that a projection area of the integrated antenna is offset from or partly overlapping with a projection area of the at least one chip;
wherein the contacting layer comprises a reflector and/or the reflector is arranged on a side facing away from the antenna; and
wherein at least one shielding via is laterally arranged between a main radiation surface of the at least one integrated antenna and the at least one chip, wherein the at least one shielding via is configured to establish shielding between the integrated antenna and the at least one chip.
1 Assignment
0 Petitions
Accused Products
Abstract
A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.
-
Citations
24 Claims
-
1. Wafer level package with integrated antenna, comprising:
-
a contacting layer; a redistribution layer with the integrated antenna; a chip layer comprising at least one chip arranged between the contacting layer and the redistribution layer; wherein the integrated antenna is laterally arranged in the redistribution layer such that a projection area of the integrated antenna is offset from or partly overlapping with a projection area of the at least one chip; wherein the contacting layer comprises a reflector and/or the reflector is arranged on a side facing away from the antenna; and wherein at least one shielding via is laterally arranged between a main radiation surface of the at least one integrated antenna and the at least one chip, wherein the at least one shielding via is configured to establish shielding between the integrated antenna and the at least one chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. Method for manufacturing a wafer level package with integrated antenna, comprising:
-
providing a chip layer comprising at least one chip; depositing a contacting layer onto the chip layer; and depositing a redistribution layer on the chip layer such that the redistribution layer is arranged opposite to the contacting layer, wherein the redistribution layer comprises at least the antenna; wherein the integrated antenna is arranged laterally in the redistribution layer such that a projection area of the integrated antenna is offset from or partly overlapping with the projection area of the at least one chip; wherein the contacting layer comprises a reflector and/or the reflector is arranged on a side facing away from the antenna; and wherein at least one shielding via is laterally arranged between a main radiation surface of the at least one integrated antenna and the at least one chip, wherein the at least one shielding via is configured to provide shielding between the integrated antenna and the at least one chip. - View Dependent Claims (16)
-
-
17. Wafer level package with integrated antenna, comprising:
-
a contacting layer; a redistribution layer; and a chip layer comprising at least one chip as well as the integrated antenna, wherein the antenna is configured as individual component, arranged between the contacting layer and the redistribution layer; wherein a shielding via is laterally arranged between a main radiation surface of the at least one chip and the antenna, which is configured to shield the chip and the antenna from one another. - View Dependent Claims (18, 19, 20, 21, 22, 23)
-
-
24. Method for manufacturing a wafer level package with integrated antenna, comprising:
-
providing at least one chip and at least one antenna element, wherein the antenna is configured as individual component; combining the at least one chip and the at least one antenna element to a chip layer; depositing a contacting layer on the chip layer; and depositing a redistribution layer on the chip layer such that the redistribution layer is arranged opposite to the contacting layer, laterally arranging a shielding via between the at least one chip and a main radiation surface of the antenna, which is configured to shield the chip and the antenna from one another.
-
Specification