Current mode hysteretic control with clocked ramp

• US 10,461,639 B1
• Filed: 08/23/2018
• Issued: 10/29/2019
• Est. Priority Date: 08/23/2018
• Status: Active Grant

• Current Assignee: Dialog Semiconductors (UK) Limited
• Original Assignee: Dialog Semiconductors (UK) Limited
• Inventors: Childs, Mark
• Primary Examiner(s): Laxton, Gary L
• Application Number:
  US16/110,091
• Time in Patent Office: 432 Days
• CPC Class Codes: H02M 1/0041 Control circuits in which a clock signal is selectively enabled or disabled
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03K 4/08 having sawtooth shape
• CPC Class Codes: H03K 4/48 using as active elements semiconductor devices H03K4/787 - H03K4/84 take precedence
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

Current in a switching converter is controlled using a current-mode hysteretic controller. The high-side switch (usually a PMOS) is turned off when the current in the coil exceeds a certain peak control current. The low-side switch (usually an NMOS) is turned off when the current in the coil falls below a certain valley control current. A current ramp is added to one of these control currents, either peak or valley. The current ramp is initiated by a reference clock signal, which has the effect of synchronizing the switching converter to the reference clock.

Claims

1. A current mode hysteretic control circuit, in a DC-DC switching converter, comprising:

a high-side switch, configured to turn off when a current in a coil exceeds a peak current limit.

a low-side switch, configured to turn off when the current in the coil falls below a valley current limit;

a ramp generator, configured to generate a current ramp, initiated with a reference clock signal, and reset when said valley current limit or said peak current limit is reached by said coil current, wherein said current ramp is used to lock a frequency of said switching converter; and

said switching converter configured with an offset between said peak current limit and said valley current limit, to provide hysteretic current-mode operation.

2. The circuit of claim 1, wherein said DC-DC switching converter is configured to switch with a frequency similar to said reference clock signal.

3. The circuit of claim 1, further comprising an operational transconductance amplifier configured to generate a control current, proportional to a difference between a target output voltage and an actual output voltage, and to supply said peak current limit and said valley current limit.

4. The circuit of claim 1, further comprising said coil, having one end connected between said high-side switch and said low-side switch, and another end at an output of said DC-DC switching converter.

5. The circuit of claim 1, wherein said offset is configured to be added to either or both said peak current limit and said valley current limit.

6. The circuit of claim 1, wherein said DC-DC switching converter is multi-phase.

7. The circuit of claim 1, wherein said current ramp is added to said valley current limit.

8. The circuit of claim 1, wherein said current ramp is subtracted from said peak current limit.

9. The circuit of claim 7, wherein said current ramp is configured with a slope having a similar order of magnitude to a down slope of a current in said coil, and wherein said down slope is calculated by dividing said output of said DC-DC switching converter by said coil value.

10. The circuit of claim 1, wherein said current ramp is added to said peak current limit, and is configured with a slope having a similar order of magnitude to an up slope of a current in said coil.

11. The circuit of claim 1, wherein a slope of said current ramp is configured to have a value between that of an up slope and a down slope of said coil current.

12. The circuit of claim 1, wherein said current ramp is added to said valley current limit and said peak current limit, wherein said ramp has a similar order of magnitude as a down slope of said coil current.

13. The circuit of claim 1, wherein said current ramp is added to said valley current limit, wherein said ramp has a similar order of magnitude as a slope equal to, or less than, (S1*S2)/(S2−

S1), where S1 is a positive slope of the current in the coil when the high-side switch is on, and S2 is a negative slope of the current in the coil when the low-side switch is on.

14. The circuit of claim 1, wherein said offset between said peak current limit and said valley current limit is controlled to be proportional to a calculated predicted peak-to-peak current ripple in said coil.

15. The circuit of claim 14, wherein said offset is controlled to be about 1.5 times that of said calculated predicted peak-to-peak current ripple in said coil.

16. The circuit of claim 1, where said high-side switch is a PMOS device and said low-side switch is an NMOS device.

17. A method for current mode hysteretic control, in a DC-DC switching converter, comprising:

turning off a high-side device, when a current in a coil exceeds a peak current limit;

turning off a low-side device, when the current in the coil falls below a valley current limit;

adding a current ramp to one of the current limits; and

initiating the current ramp with a reference clock signal, and resetting the current ramp when the coil current reaches the valley current limit, or the peak current limit, synchronizing a switching converter to the reference clock, providing hysteretic current-mode operation.

18. The method of claim 17, wherein said DC-DC switching converter switches with a frequency similar to that of said reference clock signal.

19. The method of claim 17, further comprising generating a control current with an operational transconductance amplifier, proportional to a difference between a target output voltage and an actual output voltage across said coil, which supplies said peak current limit and said valley current limit.

20. The method of claim 17, further comprising adding an offset to either or both said peak current limit and said valley current limit.

21. The method of claim 17, wherein said current ramp is added to said valley current limit.

22. The method of claim 17, wherein said current ramp is subtracted from said peak current limit.

23. The method of claim 21, wherein said current ramp has a slope having a similar order of magnitude to that of a down slope of a current in said coil.

24. The method of claim 19, wherein said current ramp is added to said peak current limit, and has a slope having a similar order of magnitude to an up slope of a current in said coil.

25. The method of claim 17, wherein a slope of said current ramp has a value between that of an up slope and a down slope of a current in said coil.

26. The method of claim 17, wherein said current ramp is added to said valley current limit and said peak current limit, wherein said ramp has a similar order of magnitude as a down slope of said coil current.

27. The method of claim 17, wherein said current ramp is added to said valley current limit, wherein said ramp has a similar order of magnitude as a slope equal to, or less than, (S1*S2)/(S2−

S1), where S1 is a positive slope of the current in the coil when the high-side device is on, and S2 is a negative slope of the current in the coil when the low-side device is on.

28. The method of claim 17, wherein an offset between said peak current limit and said valley current limit is proportional to a calculated predicted peak-to-peak current ripple in said coil.

29. The method of claim 28, wherein said offset is about 1.5 times that of said calculated predicted peak-to-peak current ripple in said coil.