Configurable clamp circuit

• US 10,461,737 B2
• Filed: 10/24/2016
• Issued: 10/29/2019
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Norling, Karl, Huber, Erwin
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/332,873
• Publication Number:
  US 20180115311A1
• Time in Patent Office: 1,100 Days
• Field of Search: 327109, 327112
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/168 in composite switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30

Abstract

In accordance with an embodiment of the present invention, a circuit includes a configurable clamp driver circuit for clamping a voltage at a gate terminal of a transistor below a turn-on voltage threshold upon switch-off of the transistor. In a first clamp driver circuit mode, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the transistor to provide a first discharge path from the gate terminal of the transistor upon switch-off of the transistor. In a second clamp driver circuit mode, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the transistor to provide a second discharge path from the gate terminal of the transistor upon switch-off of the transistor.

Claims

1. A circuit comprising:

a clamp driver circuit comprising a pull-up circuit coupled between a first power supply terminal and an output terminal of the clamp driver circuit, and a pull-down circuit coupled between a second power supply terminal and the output terminal of the clamp driver circuit;

a voltage regulator coupled between the first power supply terminal and the pull-up circuit; and

a logic circuit coupled to the pull-up circuit and the pull-down circuit, the logic circuit comprising a clamp driver configuration input and a clamp driver input, wherein the logic circuit is configured to;

operate the pull-up circuit and the pull-down circuit according to a first polarity when the clamp driver configuration input is in a first state, and

operate the pull-up circuit and the pull-down circuit according to a second polarity opposite the first polarity and deactivate the voltage regulator when the clamp driver configuration input is in a second state different from the first state.

2. The circuit of claim 1, further comprising a power transistor having a control node coupled to the output terminal of the clamp driver circuit.

3. The circuit of claim 2, wherein the control node of the power transistor is directly connected to the output terminal of the clamp driver circuit.

4. The circuit of claim 2, further comprising an external clamp transistor coupled between the control node of the power transistor and the output terminal of the clamp driver circuit.

5. The circuit of claim 2, further comprising an external clamp circuit, the external clamp circuit comprising an external transistor, wherein the control node of the external transistor is coupled to the output terminal of the clamp driver circuit and an output terminal of the external transistor is coupled to the control node of the power transistor.

6. The circuit of claim 2, wherein the power transistor is external to the clamp driver circuit.

7. The circuit of claim 2, wherein the power transistor is an IGBT.

8. The circuit of claim 2, wherein the clamp driver circuit is configured to dissipate current from the control node of the power transistor.

9. The circuit of claim 1, wherein the clamp driver circuit is disposed on a semiconductor substrate.

10. The circuit of claim 1, wherein the pull-up circuit comprises a p-channel MOSFET and the pull-down circuit comprises an n-channel MOSFET.

11. The circuit of claim 1, further comprising a voltage limiter circuit coupled between the first power supply terminal and the pull-up circuit of the clamp driver circuit.

12. The circuit of claim 11, wherein the voltage limiter circuit comprises a Zener diode.

13. The circuit of claim 1, further comprising a controller coupled to the clamp driver circuit, wherein the controller is configured to send a first control signal to the clamp driver circuit to control whether the clamp driver circuit is configured to operate according to the first polarity or according to the second polarity.

14. The circuit of claim 1, further comprising a voltage limiting circuit coupled to the clamp driver circuit and configured to limit the voltage at the output terminal of the clamp driver circuit.

15. The circuit of claim 14, wherein the voltage limiting circuit comprises a Zener diode.

16. A method of operating a configurable clamp driver circuit, the method comprising:

configuring the clamp driver circuit, comprising

receiving a control signal;

configuring a selectable polarity of a clamping signal output by the clamp driver circuit at an output terminal based on the received control signal;

configuring the clamp driver circuit by coupling the output terminal of the clamp driver circuit to a gate terminal of an external clamp transistor, wherein an output terminal of the external clamp transistor is coupled to the gate terminal of a first transistor;

switching off the first transistor; and

activating the clamp driver circuit according to the configured selectable polarity; and

deactivating a voltage regulator coupled between a power supply terminal and an output stage of the clamp driver circuit.

17. The method of claim 16, further comprising limiting a voltage at the output terminal of the clamp driver circuit.

18. The method of claim 16, wherein activating the clamp driver circuit comprises providing a low-resistance path from the gate terminal of the first transistor to a voltage supply.

19. A method of operating a clamp driver circuit comprising a pull-up circuit coupled between a first power supply terminal and an output terminal of the clamp driver circuit, and a pull-down circuit coupled between a second power supply terminal and the output terminal of the clamp driver circuit;

a voltage regulator coupled between the first power supply terminal and the pull-up circuit; and

a logic circuit coupled to the pull-up circuit and the pull-down circuit, the logic circuit comprising a clamp driver configuration input and a clamp driver input, the method comprising;

using the logic circuit, operating the pull-up circuit and the pull-down circuit according to a first polarity when the clamp driver configuration input is in a first state; and

using the logic circuit, operating the pull-up circuit and the pull-down circuit according to a second polarity opposite the first polarity and deactivate the voltage regulator when the clamp driver configuration input is in a second state different from the first state.