Ground intermediation for inter-domain buffer stages

• US 10,461,749 B1
• Filed: 10/25/2018
• Issued: 10/29/2019
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Shenzhen Goodix Technology Co., Ltd.
• Original Assignee: Shenzhen Goodix Technology Co., Ltd.
• Inventors: Moazzami, Kaveh, Hussein, Faisal, Emira, Ahmed
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US16/171,357
• Time in Patent Office: 369 Days
• Field of Search: None
• CPC Class Codes: H03F 2200/186 the ground, reference potential being controlled
• CPC Class Codes: H03F 2203/45582 the IC comprising one or more voltage sources as level shifters
• CPC Class Codes: H03F 2203/45592 the IC comprising one or more buffer stages other than emitter or source followers between the input signal leads and input leads of the dif amp, e.g. inverter stages
• CPC Class Codes: H03F 2203/45596 the IC comprising one or more biasing resistors
• CPC Class Codes: H03F 2203/45622 the IC comprising a voltage generating circuit
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.

Claims

1. An integrated circuit system comprising:

a ground intermediating buffer subsystem comprising;

a ground intermediator circuit coupled between a first circuit ground of a first circuit domain and a second circuit ground of a second circuit domain to generate an intermediated ground, such that operation of the first circuit domain produces a first quantity of ground noise on the first circuit ground, operation of the second circuit domain produces a second quantity of ground noise on the second circuit ground, and the intermediated ground is generated to have a third quantity of ground noise between the first quantity of ground noise and the second quantity of ground noise; and

a signal buffer circuit referenced to the intermediated ground and having a buffer output generated responsive to a buffer input, the buffer input coupled with a signal output node of the first circuit domain, and the buffer output coupled with a signal input node of the second circuit domain.

2. The integrated circuit system of claim 1, wherein the ground intermediator circuit comprises a resistor having a first side coupled with the first circuit ground, and a second side coupled with the second circuit ground, such that the intermediated ground is at one of the first side or the second side of the resistor.

3. The integrated circuit system of claim 2, wherein the resistor is a variable resistor.

4. The integrated circuit system of claim 1, wherein:

the first circuit domain is driven by a first supply voltage;

the second circuit domain is driven by a second supply voltage;

the ground intermediating buffer subsystem further comprises a supply voltage intermediator circuit coupled between the first supply voltage and the second supply voltage to generate an intermediated supply voltage; and

the signal buffer circuit is driven by the intermediated supply voltage.

5. The integrated circuit system of claim 4, wherein:

the ground intermediating buffer subsystem comprises a first bypass capacitor coupled between the first supply voltage and the first circuit ground, and a second bypass capacitor coupled between the second supply voltage and the second circuit ground.

6. The integrated circuit system of claim 1, wherein:

the signal buffer circuit comprises a pair of inverters referenced to the intermediated ground, at least one of the pair of inverters being a self-biased inverter.

7. The integrated circuit system of claim 1, wherein:

a ground intermediating buffer subsystem comprises a plurality of ground intermediator circuits and a plurality of signal buffer circuits;

the ground intermediator circuit is a first ground intermediator circuit of the plurality of ground intermediator circuits coupled with the first circuit ground to generate a first intermediated ground to have the third quantity of ground noise between the first quantity of ground noise and the second quantity of ground noise;

a second ground intermediator circuit of the plurality of ground intermediator circuits is coupled between the first intermediated ground and the second circuit ground to generate a second intermediated ground to have a fourth quantity of ground noise between the third quantity of ground noise and the second quantity of ground noise;

the signal buffer circuit is a first signal buffer circuit of the plurality of signal buffer circuits referenced to the first intermediated ground and having a first buffer output generated responsive to a first buffer input coupled with the signal output node; and

a second signal buffer circuit of the plurality of signal buffer circuits is referenced to the second intermediated ground and has a second buffer output generated responsive to a second buffer input coupled with the first buffer output, the second buffer output coupled with the signal input node.

8. The integrated circuit system of claim 1, wherein the first quantity of ground noise is greater than the second quantity of ground noise.

9. The integrated circuit system of claim 1, further comprising:

the first circuit domain; and

the second circuit domain.

10. The integrated circuit system of claim 9, further comprising:

a chip having a master ground node,

wherein each of the first and second circuit domains is a respective radiofrequency circuit disposed on the chip,

wherein the first circuit ground is coupled with the master ground node, and

wherein the second circuit ground is coupled with the master ground node.

11. A ground intermediating buffer comprising:

means for generating an intermediated ground responsive to a first circuit ground of a first circuit domain and a second circuit ground of a second circuit domain, wherein operation of the first circuit domain produces a first quantity of ground noise on the first circuit ground and operation of the second circuit domain produces a second quantity of ground noise on the second circuit ground, and the intermediated ground is generated to have a third quantity of ground noise that is between the first quantity of ground noise and the second quantity of ground noise; and

means for relaying a radiofrequency signal comprising;

means for receiving the radiofrequency signal from the first circuit domain;

means for buffering the radiofrequency signal referenced to the intermediated ground to output a buffered signal corresponding to the radiofrequency signal; and

means for transmitting the buffered signal to the second circuit domain.

12. The ground intermediating buffer of claim 11, wherein:

the means for generating comprise means for generating a plurality of intermediated grounds ranging from a first intermediated ground to an Nth intermediated ground, the first intermediated ground coupled most closely to the first circuit ground, and the Nth intermediated ground coupled most closely to the second circuit ground,

wherein each of the N intermediated grounds generated to have a different respective quantity of ground noise, such that, for any Kth one of the N intermediated grounds (G_K), the respective quantity of ground noise of G_K is closer to the first quantity of ground noise, and the respective quantity of ground noise of G_K+1 is closer to the second quantity of ground noise.

13. The ground intermediating buffer of claim 12, wherein the respective quantity of ground noise for each G_K differs from the respective quantity of ground noise of each G_K+1 by a substantially constant noise delta.

14. The ground intermediating buffer of claim 11, wherein:

the means for generating is responsive to the first circuit ground and the second circuit ground to dynamically adjust the third quantity of ground noise to stay between the first quantity of ground noise and the second quantity of ground noise in response to a change in the first quantity of ground noise and/or the second quantity of ground noise.

15. The ground intermediating buffer of claim 11, further comprising:

means for generating an intermediated supply voltage responsive to a first supply voltage of the first circuit domain and a second supply voltage of the second circuit domain,

wherein means for buffering is driven by the intermediated supply voltage.

16. The ground intermediating buffer of claim 15, wherein:

the means for generating the intermediated supply voltage comprise means for generating a plurality of intermediated supply voltages ranging from a first intermediated supply voltage to an Nth intermediated supply voltage, the first intermediated supply voltage coupled most closely to the first supply voltage and having a respective voltage level closest to that of the first supply voltage relative to all others of the plurality of intermediated supply voltages, and the Nth intermediated supply voltage coupled most closely to the second supply voltage and having a respective voltage level closest to that of the second supply voltage relative to all others of the plurality of intermediated supply voltages.

17. A method for ground intermediating buffering, the method comprising:

generating an intermediated ground responsive to a first circuit ground of a first circuit domain and a second circuit ground of a second circuit domain, wherein operation of the first circuit domain produces a first quantity of ground noise on the first circuit ground and operation of the second circuit domain produces a second quantity of ground noise on the second circuit ground, and the intermediated ground is generated to have a third quantity of ground noise that is between the first quantity of ground noise and the second quantity of ground noise;

receiving a radiofrequency signal from the first circuit domain;

buffering the radiofrequency signal in reference to the intermediated ground to output a buffered signal corresponding to the radiofrequency signal; and

transmitting the buffered signal to the second circuit domain.

18. The method of claim 17, wherein:

the generating comprises generating a plurality of intermediated grounds ranging sequentially from a first intermediated ground to an Nth intermediated ground, such that any Kth one of the N intermediated grounds in sequence (G_K) has a respective quantity of ground noise that is closer to the first quantity of ground noise than that of any next one of the N intermediated grounds in sequence (G_K+1).

19. The method of claim 17, wherein:

the generating comprises dynamically adjusting the third quantity of ground noise to stay between the first quantity of ground noise and the second quantity of ground noise in response to a change in the first quantity of ground noise and/or the second quantity of ground noise.

20. The method of claim 17, further comprising:

generating an intermediated supply voltage responsive to a first supply voltage of the first circuit domain and a second supply voltage of the second circuit domain,

wherein the buffering is driven by the intermediated supply voltage.