FE-FET-based XNOR cell usable in neuromorphic computing

• US 10,461,751 B2
• Filed: 09/20/2018
• Issued: 10/29/2019
• Est. Priority Date: 03/08/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Obradovic, Borna J., Hatcher, Ryan M., Kittl, Jorge A., Rakshit, Titash
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US16/137,227
• Publication Number:
  US 20190280694A1
• Time in Patent Office: 404 Days
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

Claims

1. A computing cell for performing a XNOR operation of an input signal with a weight comprising:

at least one pair of FE-FETs coupled with a plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, the first FE-FET and the second FE-FET being coupled to form a dynamic storage node;

a plurality of selection transistors coupled with the at least one pair of FE-FETs; and

a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node, the reset transistor gate being coupled with a reset line.

2. The computing cell of claim 1 wherein the plurality of selection transistors includes a first selection transistor and a second selection transistor, each of the selection transistors including a gate, a source and a drain, the source of the first selection transistor being connected a first gate of the first FE-FET, the source of the second selection transistor being connected to a second gate of the second FE-FET, the gate of the first selection transistor and the gate of the second selection transistor being coupled to a select line.

3. The computing cell of claim 2 wherein the drain of the first selection transistor is coupled with a program line and the drain of the second selection transistor is coupled with a program complement line.

4. The computing cell of claim 1 wherein the first FE-FET includes a first drain and a first source coupled with a first input line of the plurality of input lines and wherein the second FE-FET includes a second source coupled with a second input line of the plurality of input lines and a second drain, the second drain being coupled with the first drain to provide the dynamic storage node.

5. The computing cell of claim 1 wherein the first FE-FET includes a first ferroelectric material, the second FE-FET includes a second ferroelectric material, the first ferroelectric material and the second ferroelectric material including at least one of PbZrTi, HfZrO, BaTiO₃, B₁₂TiO₂₀, GeTe, and Ba_xEu_1-xTiO₃, where x is greater than zero and not more than one.

6. The computing cell of claim 1 wherein the first weight and the second weight complement are complements for the weight being nonzero and equal for the weight being zero.

7. The computing cell of claim 1 wherein the plurality of FE-FET transistors consists of the first FE-FET and the second FE-FET and the plurality of selection transistors consists of a first selection transistor and a second selection transistor.

8. A computing cell for performing a XNOR operation of an input signal with a weight comprising:

at least one pair of FE-FETs coupled with a plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, the first FE-FET including a first drain and a first source coupled with a first input line of the plurality of input lines, the second FE-FET including a second source coupled with a second input line of the plurality of input lines and a second drain, the second drain being coupled with the first drain to provide a dynamic storage node;

a plurality of selection transistors coupled with the at least one pair of FE-FETs; and

a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node, the reset transistor gate being coupled with a reset line.

9. A neural network comprising:

a plurality of input lines;

a plurality of XNOR cells, each of the plurality of XNOR cells for performing a digital XNOR operation of an input signal with a weight, each of the plurality of XNOR cells including at least one pair of FE-FETs, a plurality of selection transistors coupled with the at least one pair of FE-FETs and a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the at least one pair of FE-FETs coupled with a portion of the plurality of input lines and storing the weight, the at least one-pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, the first FE-FET and the second FE-FET being coupled to form a dynamic storage node, the reset transistor source being connected to the dynamic storage node, the reset transistor gate being coupled with a reset line.

10. The neural network of claim 9 wherein the plurality of selection transistors includes a first selection transistor and a second selection transistor, each of the selection transistors including a gate, a source and a drain, the source of the first selection transistor being connected a first gate of the first FE-FET, the source of the second selection transistor being connected to a second gate of the second FE-FET, the gate of the first selection transistor and the gate of the second selection transistor being coupled to a select line, the drain of the first selection transistor is coupled with a program line and the drain of the second selection transistor is coupled with a program complement line and wherein the plurality of FE-FETs consists of the first FE-FET and the second FE-FET.

11. The neural network of claim 10 wherein the first FE-FET includes a first drain and a first source coupled with a first input line of the plurality of input lines and wherein the second FE-FET includes a second drain and a second source coupled with a second input line of the plurality of input lines, the first drain being coupled with the second drain to form the dynamic storage node.

12. The neural network of claim 9 wherein the first FE-FET includes a first ferroelectric material, the second FE-FET includes a second ferroelectric material, the first ferroelectric material and the second ferroelectric material including at least one of PbZrTi, HfZrO, BaTiO₃, B₁₂TiO₂₀, GeTe, and Ba_xEu_1-xTiO₃, where x is greater than zero and not more than one, and wherein the first ferroelectric material and the second ferroelectric material are integrated at a first metal layer or higher for the neural network.

13. A neural network comprising:

a plurality of input lines;

a plurality of XNOR cells, each of the plurality of XNOR cells for performing a digital XNOR operation of an input signal with a weight, each of the plurality of XNOR cells including at least one pair of FE-FETs and a plurality of selection transistors coupled with the at least one pair of FE-FETs, the at least one pair of FE-FETs coupled with a portion of the plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, the first FE-FET including a first drain and a first source coupled with a first input line of the plurality of input lines, the second FE-FET including a second drain and a second source coupled with a second input line of the plurality of input lines, the first drain being coupled with the second drain to form a dynamic storage node; and

wherein each of the plurality of XNOR cells further includes

a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node and wherein the neural network further includes

a plurality of reset lines, each of the plurality of reset lines being coupled with the reset transistor gate of at least one of the plurality of XNOR cells.

14. A method for performing a digital XNOR operation comprising:

providing an input signal and the input signal complement to an XNOR cell for performing a digital XNOR operation of the input signal with a weight, the XNOR cell including at least one pair of FE-FETs, a plurality of selection transistors coupled with the at least one pair of FE-FETs and a reset transistor, the at least one pair of FE-FETs coupled with a plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, the first FE-FET and the second FE-FET being coupled to form a dynamic storage node, the reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node, the reset transistor gate being coupled with a reset line.

15. A method for performing a digital XNOR operation comprising:

providing an input signal and the input signal complement to an XNOR cell for performing a digital XNOR operation of the input signal with a weight, the XNOR cell including at least one pair of FE-FETs and a plurality of selection transistors coupled with the at least one pair of FE-FETs, the at least one pair of FE-FETs coupled with a plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, wherein the plurality of selection transistors includes a first selection transistor and a second selection transistor, the plurality of FE-FETS consists of the first FE-FET and the second FE-FET, each of the selection transistors including a gate, a source and a drain, the source of the first selection transistor being connected a first gate of the first FE-FET, the source of the second selection transistor being connected to a second gate of the second FE-FET, the drain of the first selection transistor being coupled with a program line, the drain of the second selection transistor being coupled with a program complement line, the gate of the first selection transistor and the gate of the second selection transistor being coupled to a select line; and

programming the first weight and the second weight into the first FE-FET and the second FE-FET, the step of programming the first weight and the second weight further including

erasing the first FE-FET and the second FE-FET by setting the program line to a ground, setting the program complement line to the ground, setting the select line to a high state, setting an input line and an input complement line of the plurality of input lines to the high state; and

writing to the first FE-FET and the second FE-FET after the erasing step by setting the input signal line to the ground, setting the input signal complement line to the ground, setting the select line to the high state, and one of pulsing the programming line, pulsing the program complement line and pulsing neither of the program line and the program complement line.

16. The method of claim 15 wherein the programming step uses non-negative voltages.

17. The method of claim 15 wherein the step of providing the input signal further includes:

implementing a reset step and an evaluate step.

18. The method of claim 17 wherein the first FE-FET includes a first drain and a first source coupled with a first input line of the plurality of input lines, wherein the second FE-FET includes a second source coupled with a second input line of the plurality of input lines and a second drain, the second drain being coupled with the first drain to provide a dynamic storage node and wherein the XNOR cell further includes a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node, the reset transistor being coupled to a reset line, the method further comprising:

pulsing the reset line before the evaluate step.

19. The method of claim 17 further comprising:

pulsing the program line, the program complement line and the select line high before the evaluate step.

20. The method of claim 15 wherein the step of providing the input signal further includes:

setting the select line to the low state;

providing the input signal on the input line and the input complement signal on the input complement line while the select line is in a low state.