Techniques for configurable ADC front-end RC filter

• US 10,461,770 B2
• Filed: 06/22/2018
• Issued: 10/29/2019
• Est. Priority Date: 07/13/2017
• Status: Active Grant

• Current Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Gutta, Avinash, Nittala, Venkata Aruna Srikanth
• Primary Examiner(s): Jean Pierre, Peguy
• Application Number:
  US16/015,585
• Publication Number:
  US 20190020352A1
• Time in Patent Office: 494 Days
• Field of Search: 341155, 341122118, 341120
• CPC Class Codes: H03H 1/02 of RC networks, e.g. integrated networks
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03H 7/06 including resistors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/425 Balance-balance networks
• CPC Class Codes: H03M 3/322 Continuously compensating for, or preventing, undesired influence of physical parameters periodically, e.g. by using stored correction values, H03M3/378
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
• CPC Class Codes: H03M 3/392 Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
• CPC Class Codes: H03M 3/422 having one quantiser only
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input
• CPC Class Codes: H03M 3/494 Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems

Abstract

Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

Claims

1. A front-end circuit for suppressing signal transfer function peaking of a processing circuit, the front-end circuit comprising:

a resistor-capacitor filter including at least two capacitors, the resistor-capacitor filter configured to couple an input analog signal to the processing circuit;

a switch circuit coupled to a first capacitor of the at least two capacitors, the switch circuit configured to selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter; and

wherein the resistor-capacitor filter comprises;

a first set of series-connected resistances configured to couple a first differential input terminal with a first input of the processing circuit;

, and

a second set of series-connected resistances configured to couple a second differential input terminal with a second input of the processing circuit.

2. The circuit of claim 1, wherein the first and second differential input terminals of the resistor-capacitor filter are configured to receive the input analog signal.

3. The front-end circuit of claim 2, wherein the processing circuit includes an analog-to-digital converter (ADC).

4. The circuit of claim 3, wherein the at least two capacitors are configured to couple between nodes of the first set of series-connected resistances and the second set of series-connected resistances;

wherein a second capacitor of the at least two capacitors is configured to couple between the first set of series-connected resistances and the second set of series-connected resistances at first nodes of sets of series-connected resistances, wherein the first nodes are located further along an electrical path of the resistor-capacitor filter from the first integrator than the selected one of the plurality of distinct nodes to which the first capacitor is selectively coupled; and

wherein a first resistance of the first set of series-connected resistances is configured to couple between the terminal of the first capacitor and the first input of the first integrator; and

wherein the first resistance has a lowest resistance value of the first set of series-connected resistances.

5. The circuit of claim 3, wherein a first resistance of the first set of series-connected resistances and a first resistance of the second set of series connected resistances are electrically coupled closer to the first integrator than the other resistances of the first set of series-connected resistances and the second set of series connected resistances;

and

wherein the first resistances are adjustable in resistance value to suppress signal transfer function peaking of the ADC.

6. The circuit of claim 3, wherein the switch circuit is configured to adjust states in response to a condition of the AI)C;

and

wherein the condition is a manufacturing anomaly of the ADC.

7. The circuit of claim 3, wherein the switch circuit is configured to adjust states in response to a condition of the ADC;

and

wherein the condition is a clock frequency of the ADC.

8. The circuit of claim 7, wherein the switch circuit, in a first state, is configured to couple the terminal of the first capacitor at a first distinct node of the plurality of distinct nodes when the condition of the ADC is lower than a first threshold value;

wherein the switch circuit, in a second state, is configured to couple the terminal of the first capacitor at a second distinct node of the plurality of distinct nodes when the condition of the ADC is higher than the first threshold value

wherein a first resistance of the resistor-capacitor filter is coupled between the first distinct node and the second distinct node,

wherein the first distinct node is electrically coupled closer to the processing circuit than the second distinct node; and

wherein a second resistance of the first set of series-connected resistances is electrically coupled between the first terminal of the first capacitor and a first terminal of the second capacitor when the switch circuit is in the second state.

21. The front-end circuit of claim 1, wherein the switch circuit is further configured to selectively couple a first capacitor of the at least two capacitors with an intermediate node of the first set of series-connected resistances.

9. A front-end circuit for suppressing signal transfer function peaking of an analog-to-digital converter (ADC), the circuit comprising:

a plurality of resistor-capacitor (RC) filters selectively coupled in parallel with each other, the plurality of RC filters configured to couple an input analog signal with an integrator of the ADC; and

wherein each resistor-capacitor filter includes at least two capacitors; and

wherein a first capacitor of the at least two capacitors is electrically coupled closer to the integrator than a second capacitor of the at least two capacitors.

10. The front-end circuit of claim 9, wherein the plurality of RC filters are configured to receive a single-ended input analog signal.

11. The front-end circuit of claim 9, wherein the plurality of RC filters are configured to receive a differential input analog signal.

12. The front-end circuit of claim 9, wherein the plurality of RC filters include a first set of one or more RC filters and a second set of one or more RC filters;

and

wherein a first capacitor of each of the first set of one or more RC filters has less capacitance than the corresponding first capacitor of each of the second set of one or more RC filters.

13. The front-end circuit of claim 12, wherein each RC filter of the plurality of RC filters includes a switch circuit, the switch circuit configured to enable and disable a peak suppression effect of the corresponding RC filter.

14. The front-end circuit of claim 13, wherein the switch circuit of an individual one of the first set of one or more RC filters is configured to enable the peak suppression effect when an operating clock frequency of the ADC is above a first threshold value and to disable the peaking suppression effect when the operating clock frequency of the ADC is below a second threshold value;

and

wherein the switch circuit of an individual one of the second set of one or more RC filters is configured to enable the peaking suppression effect when the operating clock frequency of the ADC is below the second threshold value and to disable the peaking suppression effect when the operating clock frequency of the ADC is above the first threshold value.

15. The front-end circuit of claim 13, wherein the switch circuit of an individual one of the first set of one or more RC filters is configured to enable the peaking suppression effect when an operating clock frequency of the ADC is above a first threshold value and to disable the peaking suppression effect when the operating clock frequency of the ADC is below a second threshold value;

and

wherein the switch circuit of an individual one of the second set of one or more RC filters is configured to enable the peaking suppression effect when the operating clock frequency of the ADC is below the second threshold value and to disable the peaking suppression effect when the operating clock frequency of the ADC is above the first threshold value.

22. The front-end circuit of claim 9, wherein at least one RC filter of the plurality of RC filters includes:

a set of series-connected resistances configured to couple the input analog signal with an integrator of the ADC; and

a switch circuit configured to selectively couple the first capacitor with an intermediate node of the set of series-connected resistances.

16. A system to enhance an analog-to-digital converter (ADC) transfer function by adjusting a front-end filter circuit, the system comprising:

an ADC; and

a configurable resistor-capacitor filter having at least two capacitors, the configurable resistor-capacitor filter configured to receive an analog input signal, to pass the analog input signal to a first integrator of the ADC, and to suppress signal transfer function peaking of the ADC.

17. The system of claim 16, wherein the ADC includes a feedforward ADC having a signal transfer function peak at an operating clock frequency of the feedforward ADC.

18. The system of claim 16, wherein the ADC includes a sigma-delta ADC having a signal transfer function peak at an operating clock frequency of the sigma-delta ADC.

19. The system of claim 16, wherein the ADC includes a feedforward, sigma-delta ADC having a signal transfer function peak at an operating clock frequency of the feedforward, sigma-delta ADC.

20. The system of claim 16, wherein the configurable resistor-capacitor filter includes differential input terminals, the differential input terminals configured to receive the analog input signal.

23. The system of claim 16, wherein the configurable resistor-capacitor filter includes:

a set of series-connected resistances configured to couple the input analog signal with an input of the ADC; and

a switch circuit configured to selectively couple the first capacitor with an intermediate node of the set of series-connected resistances.