Error locator polynomial decoder and method

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First Claim
1. A decoding apparatus comprising:
 a syndrome generator circuit configured to receive data and generate at least two different sets of syndromes;
an error locator polynomial generator circuit configured to receive the at least two different sets of syndromes and generate a mutual error locator polynomial; and
a convergence detector circuit coupled to the error locator polynomial generator circuit, the convergence detector circuit including;
at least two computation circuits configured to generate at least two convergence signals based on the mutual error locator polynomial from the error locator polynomial generator circuit and on the at least two different sets of syndromes, wherein each of the different sets of syndromes corresponds to a different one of the convergence signals.
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Abstract
An apparatus includes a convergence detector circuit coupled to an error locator polynomial generator circuit. The convergence detector circuit includes at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes. Each of the different sets of syndromes corresponds to a different one of the convergence signals.
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20 Claims
 1. A decoding apparatus comprising:
a syndrome generator circuit configured to receive data and generate at least two different sets of syndromes; an error locator polynomial generator circuit configured to receive the at least two different sets of syndromes and generate a mutual error locator polynomial; and a convergence detector circuit coupled to the error locator polynomial generator circuit, the convergence detector circuit including; at least two computation circuits configured to generate at least two convergence signals based on the mutual error locator polynomial from the error locator polynomial generator circuit and on the at least two different sets of syndromes, wherein each of the different sets of syndromes corresponds to a different one of the convergence signals.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
 11. A decoding apparatus comprising:
means for generating first and second sets of syndromes; means for generating an error locator polynomial; means for generating a first convergence signal based on the error locator polynomial and corresponding to the first set of syndromes; means for generating, concurrently with generation of the first convergence signal, a second convergence signal based on the error locator polynomial and corresponding to the second set of syndromes; and means for generating a nonconvergence indicator in response to at least one of the first convergence signal and the second convergence signal indicating nonconvergence, and generating a convergence indicator in response to all received convergence signals indicating convergence.  View Dependent Claims (12, 13)
 14. A decoding apparatus comprising:
a syndrome generator circuit for receiving data and generating sets of syndromes; an error locator polynomial generator circuit; and a convergence detector circuit coupled to the error locator polynomial generator circuit, the convergence detector circuit including; at least three computation circuits configured to generate at least three convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least three different sets of syndromes, wherein each of the different sets of syndromes corresponds to a different one of the convergence signals.  View Dependent Claims (15, 16, 17, 18, 19, 20)
1 Specification
This application is a continuationinpart of U.S. Nonprovisional application Ser. No. 15/343,866 filed Nov. 4, 2016 and entitled “METHOD AND DECODER TO ADJUST AN ERROR LOCATOR POLYNOMIAL BASED ON AN ERROR PARITY”. This application is also a continuationinpart of U.S. Nonprovisional application Ser. No. 14/963,025, filed on Dec. 8, 2015, which claims priority to and the benefit of U.S. Provisional Application No. 62/192,513, filed on Jul. 14, 2015 and entitled, “SYSTEMS AND METHODS FOR PROVIDING LOW LATENCY READ PATH FOR NONVOLATILE MEMORY”. The entire content of each of these applications is incorporated herein by reference.
This disclosure is generally related to electronic devices and more particularly to decoders of electronic devices.
Data storage devices enable users to store and retrieve data. Examples of data storage devices include volatile memory devices and nonvolatile memory devices. A nonvolatile memory may retain data after a powerdown event, and a volatile memory may lose data after a powerdown event.
In some cases, data may be subject to one or more errors. For example, electrical noise may cause a logic “0” value to be read as a logic “1” value (or vice versa). Electrical noise may affect data within an electronic device as well as data that is sent via a network, such as a wireless network or a wired network. For example, a mobile phone may receive data that is affected by a wireless channel used to receive the data.
To enable correction of data errors, an encoder may encode data using an encoding scheme, such as by adding redundancy information to the data prior to storing the data to a memory or prior to transmitting the data. The encoding scheme may specify a codebook that associates data with codewords of the encoding scheme. A decoder may decode the data by using the redundancy information to locate and correct one or more data errors (up to a particular error correction capability of the encoding scheme).
Decoding data consumes power and clock cycles of a device. For example, a decoder may use an iterative decoding process to locate data errors, which utilizes power and one or more clock cycles for each iteration.
A device is configured to decode data using a decoding process that includes adjusting a length of an error locator polynomial based on an error parity associated with the data. As an illustrative example, by encoding the data using an “even” codebook that includes codewords each having an even number of logic “1” values, the device may determine whether a sensed representation of the data includes an even number of errors of an odd number of errors (i.e., whether the error parity is odd or even).
The error parity may enable the device to “condense” certain operations of a decoding process. For example, a decoding process may include iteratively adjusting the length of the error locator polynomial and checking whether the adjusted length is “correct” based on syndrome information associated with the data. In this example, the error parity may enable the device to adjust the length of the error locator polynomial by a value of two in some cases. To illustrate, if the length of the error locator polynomial is even (based on the error parity of the data to be decoded), then the device may “skip” adjusting the length to an odd number in some circumstances (e.g., by adjusting the length from a value of two to a value of four, as an illustrative example). Alternatively, if the length of the error locator polynomial is odd (based on the error parity of the data to be decoded), then the device may “skip” adjusting the length to an even number in some circumstances.
Use of the error parity to adjust the length of the error locator polynomial may reduce a number of clock cycles used to decode data. As a result, decoding latency and power consumption may be reduced.
Particular aspects of the disclosure are described below with reference to the drawings. In the description, common or similar features may be designated by common reference numbers. As used herein, “exemplary” may indicate an example, an implementation, and/or an aspect, and should not be construed as limiting or as indicating a preference or a preferred implementation.
Referring to
The memory device 103 includes a memory 104, such as a nonvolatile array of storage elements included in one or more memory dies. The memory 104 may include a flash memory (e.g., a NAND flash memory) or a resistive memory, such as a resistive random access memory (ReRAM), as illustrative examples. The memory 104 may have a threedimensional (3D) memory configuration. As used herein, a 3D memory device may include multiple physical levels of storage elements (instead of having a single physical level of storage elements, as in a planar memory device). As an example, the memory 104 may have a 3D vertical bit line (VBL) configuration. In a particular implementation, the memory 104 is a nonvolatile memory having a 3D memory array configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. Alternatively, the memory 104 may have another configuration, such as a twodimensional (2D) memory configuration or a nonmonolithic 3D memory configuration (e.g., a stacked die 3D memory configuration).
The memory 104 includes one or more regions of storage elements. An example of a storage region is a block, such as a NAND flash erase group of storage elements, or a group of resistancebased storage elements in a ReRAM implementation. Another example of a storage region is a word line of storage elements (e.g., a word line of NAND flash storage elements or a word line of resistancebased storage elements). A storage region may have a singlelevelcell (SLC) configuration, a multilevelcell (MLC) configuration, or a trilevelcell (TLC) configuration, as illustrative examples. Each storage element of the memory 104 may be programmable to a state (e.g., a threshold voltage in a flash configuration or a resistive state in a resistive memory configuration) that indicates one or more values. As an example, in an illustrative TLC scheme, a storage element may be programmable to a state that indicates three values. As an additional example, in an illustrative MLC scheme, a storage element may be programmable to a state that indicates two values.
The controller 130 includes a memory interface 132 to the memory device 103 and further includes a device interface 172 to the device 170. The controller 130 also includes a circuit 140 and a decoder 150. The circuit 140 is coupled to the decoder 150. The controller 130 further includes an encoder 160.
The encoder 160 is configured to encode data to generate one or more error correcting code (ECC) codewords using one or more ECC encoding techniques. The encoder 160 may be configured to encode data using an algebraic code. The encoder 160 may include a ReedSolomon (RS) encoder, a BoseChaudhuriHocquenghem (BCH) encoder, an encoder configured to encode data according to one or more other ECC techniques, or a combination thereof.
The decoder 150 is configured to decode data read from the memory 104 to detect and correct, up to an error correction capability of the ECC scheme, one or more bit errors that may be present in the data. The decoder 150 may be configured to decode data using an algebraic code. The decoder 150 may include an RS decoder, a BCH decoder, a decoder configured to decode data according to one or more other ECC techniques, or a combination thereof. In some implementations, the decoder 150 is configured to operate in accordance with one or more of a BerlekampMassey (BM) technique or a PetersonGorensteinZierler (PGZ) technique.
During operation, the controller 130 may receive data 174 from the device 170, such as in connection with a request for write access to the memory 104. The controller 130 may input the data 174 to the encoder 160 to generate encoded data, such as data 106. As an illustrative example, the data 174 may be encoded in accordance with a BCH code to generate the data 106.
The data 106 may include one or more codewords associated with a codebook 162 of a particular code (e.g., a BCH code, as an illustrative example) that is used to generate the data 106. In an illustrative example, each codeword indicated by the codebook 162 may include an even number of logic one values (i.e., the codebook 162 may correspond to an “even codebook”).
The encoder 160 may be configured to generate a set of codewords each having an even number of logic one values. For example, the encoder 160 may be configured to encode the data 174 using a generator polynomial 164 having a factor 166 selected to cause each codeword of the set of codewords to have an even number of logic one values. To illustrate, the generator polynomial 164 may correspond to g(x)*(1+x), where g(x) is a generator function of a BCH code and (1+x) corresponds to the factor 166.
The controller 130 may be configured to send the data 106 to the memory device 103. The memory device 103 may store the data 106 to a particular region of the memory 104.
The controller 130 may access the data 106 from the memory 104. As an illustrative example, the controller 130 may receive a request for read access to the data 106. The controller 130 may send a read command to the memory device 103 to initiate reading of the data 106. In response to the read command, the memory device 103 may sense the data 106 to generate sensed data, such as first data 134. The first data 134 may differ from the data 106 due to one or more errors. The memory device 103 may provide the first data 134 to the controller 130.
The controller 130 may input the first data 134 to the circuit 140. For example, the circuit 140 may be coupled to the memory interface 132 and may receive the first data 134 from the memory interface 132. The circuit 140 is configured to determine an error parity 142 (also referred to herein as “p”) of the first data 134. To illustrate, if the codebook 162 corresponds to an “even” codebook, the circuit 140 may be configured to determine the error parity 142 based on whether the first data 134 indicates an even number of logic one values or an odd number of logic one values.
To further illustrate, the circuit 140 may identify (e.g., count) a number of logic one values included in the first data 134. In this example, the error parity 142 corresponds to a difference between the number of logic one values and a codeword parity that is associated with each codeword of an encoding scheme used to encode the first data 134. In an illustrative implementation, the circuit 140 is configured to set the error parity 142 to a particular logic value (e.g., a logic zero value) in response to determining that the number of logic one values included in the first data 134 is even. In this example, the circuit 140 may be further configured to set the error parity 142 to another logic value (e.g., a logic one value) in response to determining that the number of logic one values included in the first data 134 is odd.
The decoder 150 is configured to receive the first data 134 (e.g., from the circuit 140 or from the memory interface 132). The decoder 150 is further configured to receive an indication of the error parity 142 from the circuit 140. The decoder 150 is configured to decode the first data 134 to generate second data 136. The second data 136 may correspond to the data 174 (e.g., an errorcorrected version of the first data 134), as an illustrative example.
The decoder 150 is configured to generate the second data 136 by adjusting an error locator polynomial 152 (also referred to herein as “C(D)”) based on the error parity 142 of the first data 134. The error locator polynomial 152 has a length L, such as a positive integer number of coefficients of the error locator polynomial 152, as an illustrative example.
To further illustrate, the decoder 150 may be configured to perform a decoding process that includes one or more iterations to decode the first data 134. The decoding process may include adjusting the length L based on an estimated number of errors of the first data 134, such as by iteratively increasing the length L. After adjusting the length L, the decoder 150 may use the error locator polynomial 152 to correct one or more errors of the first data 134. By accessing the error parity 142, the decoder 150 may omit (or “skip”) certain iterations of the decoding process in some cases, such as by skipping adjusting the length of the error locator polynomial 152 to an even value or to an odd value based on the error parity 142 in certain iterations of the decoding process. In this case, the decoder 150 may be configured to adjust the length L by a value of two.
The decoder 150 may be configured to adjust the length L by a particular value based on a comparison of the error parity 142 to a parity of the error locator polynomial 152. For example, the decoder 150 may be configured to increase the length L by a value of two if the error parity 142 is equal to a parity of the error locator polynomial 152. As another example, the decoder 150 may be configured to increase the length L by a value of one if the error parity 142 is not equal to a parity of the error locator polynomial 152.
The decoder 150 may be configured to adjust the length L (e.g., by a value of two or by a value of one) in a single iteration of a decoding process to decode the first data 134. For example, the decoder 150 may be configured to decode the first data 134 in accordance with an improved BM technique to generate the second data 136. In this example, by increasing the length L by a value of two in certain iterations, the decoder 150 may be configured to “condense” operations of two iterations of the BM technique into a single iteration (e.g., to perform the two iterations of an improved BM decoding process in parallel). As another example, the decoder 150 may be configured to decode the first data 134 in accordance with an improved PGZ technique to generate the second data 136.
To further illustrate, the pseudocode of Example 1 illustrates certain operations that may be performed in connection with an improved BM decoding process. In order to understand the example, it may be beneficial to look first at another version of the BM algorithm for decoding primitive narrow sense BCH codes, as shown in the pseudocode of Table 1:
In the BM algorithm, for a narrow sense BCH code, each change to the length L of C(D) results in a change of the parity of the length from odd to even or from even to odd. This follows from the equation relating the “new” length (Lnew) to the current length (L): Lnew=2T+1−L.
If the “correct” parity of L is known in advance, and if the length L is updated on two successive iterations, then two iterations may be performed at once, thus reversing the parity twice (or “preserving” the parity of L during the BM algorithm). This may speed up the BM algorithm and may reduce the time for convergence of the algorithm by up to 50%. A condition is that both L≤T and Lnew=2T+1−L≤T+1, which has the solution L=T.
Therefore, if the parity of the length of the “true” C(D) is known in advance, the BM algorithm may be modified to the IBM algorithm as depicted below in example 1. The decoder 150 may be configured to operate in accordance with the pseudocode of Example 1.
In Example 1, C(D) may correspond to the error locator polynomial 152, and D may indicate a variable of the error locator polynomial. L may correspond to the degree of the error locator polynomial 152 (also referred to herein as the length of the error locator polynomial 152), and t may indicate an error correction capability associated with the particular ECC scheme. T may indicate (e.g., track) a number of iterations performed in a particular decoding process, B(D) may indicate a previous estimation of C(D) (e.g., prior to adjusting L), c_{i }may indicate the ith coefficient of C(D), b_{i }may indicate the ith coefficient of B(D), and S_{i }may indicate the ith syndrome.
During a decoding process performed in accordance with Example 1, L may be increased iteratively. In certain iterations, a first iteration and a second iteration may be performed in parallel (instead of performing the first iteration and then checking whether convergence is satisfied or if the conditions for performing the second iteration are satisfied). In this case, L may be increased by two (i.e., L=L+2). These iterations occur if the error parity p corresponds to the current estimated degree L of C(D) (i.e., if parity(L)==p) and if the iteration number T is equal to the degree L. In this case, two iterations of the decoding process may be “condensed” into a single iteration and L may be incremented by two.
By “condensing” operations of two iterations of a decoding process into a single iteration, data may be decoded more quickly. As a result, performance of the data storage device 102 may be improved.
During operation, the syndrome generator circuit 204 may receive the first data 134. The first data 134 may include k errors (where k is a positive integer number). The syndrome generator circuit 204 may be configured to generate a syndrome polynomial 206 based on the first data 134.
The error locator polynomial generator circuit 208 may be configured to receive the syndrome polynomial 206, an indication of the error parity 142, and a clock signal 202. The error locator polynomial generator circuit 208 may be configured to generate the error locator polynomial 152 based on the syndrome polynomial 206 and to adjust the length L of the error locator polynomial 152 based on the error parity 142.
The error locator polynomial generator circuit 208 may be configured to perform operations based on the clock signal 202. For example, one iteration of the while loop of Example 1 may be performed during each cycle of the clock signal 202. Generating the error locator polynomial 152 and adjusting the length L of the error locator polynomial 152 may thus be performed based on the clock signal 202. The error locator polynomial generator circuit 208 may be configured to adjust coefficients of the error locator polynomial 152 based on the syndrome polynomial 206 and based on the clock signal 202. The error locator polynomial generator circuit 208 may be configured to adjust the length L of the error locator polynomial 152 until determining that the length L is “correct” based on the syndrome polynomial 206. For example, the error locator polynomial generator circuit 208 may be configured to determine that the error locator polynomial 152 is “correct” based on a product of the error locator polynomial 152 and the syndrome polynomial 206. After adjusting the error locator polynomial 152, the error locator polynomial generator circuit 208 may provide the error locator polynomial 152 to the error corrector circuit 210.
In the example of
The error corrector circuit 210 may be configured to determine one or more error locations 212 of the first data 134 based on the error locator polynomial 152. For example, the error corrector circuit 210 may include a Chien search circuit configured to perform a Chien search of the error locator polynomial 152 to determine the one or more error locations 212 of the first data 134. In an illustrative example, the error corrector circuit 210 is configured to determine the one or more error locations 212 by determining a set of roots of the error locator polynomial 152. In certain cases (e.g., if L 4), then the roots of the error locator polynomial 152 may be solved for analytically (e.g., instead of using a Chien search).
The error corrector circuit 210 may be configured to adjust values of the first data 134 based on the one or more error locations 212 to generate the second data 136. For example, the error corrector circuit 210 may “flip” one or more bits of the first data 134 based on the one or more error locations 212 to generate the second data 136. The second data 136 may correspond to the data 174 of
The example of
Referring to
The controller 330 includes the memory interface 132 to the memory device 103 and further includes the device interface 172 to the device 170. The controller 330 also includes a decoder 350 and an encoder 360. The decoder 350 includes a first circuit 352, a second circuit 354, and a third circuit 356 coupled to the first circuit 352 and to the second circuit 354. In some implementations, the decoder 350 further includes the syndrome generator circuit 204 and the error corrector circuit 210 of
The encoder 360 is configured to encode data to generate one or more ECC codewords using one or more ECC encoding techniques. The encoder 360 may include an RS encoder, a BCH encoder, an encoder configured to encode data according to one or more other ECC techniques, or a combination thereof.
The decoder 350 is configured to decode data read from the memory 104 to detect and correct, up to an error correction capability of the ECC scheme, one or more bit errors that may be present in the data. The decoder 350 may include an RS decoder, a BCH decoder, a decoder configured to decode data according to one or more other ECC techniques, or a combination thereof.
The circuits 352, 354 may be configured to perform certain operations in parallel. To illustrate, the decoder 350 may be configured to perform multiple iterations of a BM decoding process in parallel using the circuits 352, 354.
During operation, the controller 330 may receive the data 174 from the device 170, such as in connection with a request for write access to the memory 104. The controller 330 may input the data 174 to the encoder 360 to generate encoded data, such as the data 106. As an illustrative example, the data 174 may be encoded in accordance with an RS code or in accordance with a BCH code to generate the data 106.
The controller 330 may be configured to send the data 106 to the memory device 103. The memory device 103 may store the data 106 to a particular region of the memory 104.
The controller 330 may access the data 106 from the memory 104. As an illustrative example, the controller 330 may receive a request for read access to the data 106. The controller 330 may send a read command to the memory device 103 to initiate reading of the data 106. In response to the read command, the memory device 103 may sense the data 106 to generate sensed data, such as first data 134. The first data 134 may differ from the data 106 due to one or more errors. The first data 134 may include a set of symbols (or a representation of the symbols) encoded in accordance with an RS code or a BCH code, as illustrative examples. The memory device 103 may provide the first data 134 to the controller 330.
The controller 330 may input the first data 134 to the first circuit 352 and to the second circuit 354. In an illustrative example, the controller 330 is configured to input the first data 134 to the first circuit 352 and to the second circuit 354 in parallel (e.g., during a common clock cycle of a clock signal used by the controller 330).
The decoder 150 may be configured to determine a syndrome polynomial based on the first data 134. For example, the decoder 350 may include the syndrome generator circuit 204 of
In some examples, the first data 134 includes a set of symbols (e.g., in accordance with a nonbinary encoding technique that uses symbols to represent data). In some circumstances, determining an error parity associated with a set of symbols may be inefficient or infeasible. The decoder 350 may be configured to separately “assume” both an even error parity and an odd parity of the first data 134 and to perform operations based on the even error parity and the odd error parity in parallel.
The first circuit 352 is configured to receive the first data 134 and to perform a set of decoding operations based on the first data 134 by adjusting a first error locator polynomial 358 based on an even error parity of the first data 134. In the example of
The second circuit 354 is configured to receive the first data 134 and to perform the set of decoding operations (e.g., a set of decoding operations performed in accordance with a BM decoding technique, as an illustrative example) by adjusting a second error locator polynomial 359 based on an odd error parity of the first data 134. In the example of
The third circuit 356 is configured to select an output of the first circuit 352 or the second circuit 354. For example, the first circuit 352 may be configured to provide the first error locator polynomial 358 to the third circuit 356, and the second circuit 354 may be configured to provide the second error locator polynomial 359 to the third circuit 356. The third circuit 356 may be configured to select either the first error locator polynomial 358 or the second error locator polynomial 359 based on whether the “correct” parity of the first data 134 is even or odd. For example, the third circuit 356 may be configured to select the output of the first circuit 352 or the second circuit 354 in response to detecting that the output satisfies convergence criteria associated with a code (e.g., an RS code or a BCH code) associated with the first data 134. Determining whether the convergence criteria are satisfied may include determining which of the error locator polynomials 358, 359 corresponds to the syndrome polynomial 206 of
In some implementations, the third circuit 356 may include a comparator circuit and a multiplexer (MUX) circuit coupled to the comparator circuit. The comparator circuit may be configured to determine which of the first error locator polynomial 358 and the second error locator polynomial 359 satisfies the convergence criteria. The comparator circuit may be configured to provide a signal to the MUX circuit. The signal may have one of a first value to indicate that the first error locator polynomial 358 satisfies the convergence criteria or a second value to indicate that the second error locator polynomial 359 satisfies the convergence criteria. The MUX circuit may select the first error locator polynomial 358 or the second error locator polynomial 359 based on the signal.
The third circuit 356 may be configured to perform decoding of the first data 134 based on the selected output of the circuits 352, 354 (i.e., based on the first error locator polynomial 358 or the second error locator polynomial 359). For example, the third circuit 356 may include the error corrector circuit 210 of
By determining the error locator polynomials 358, 359 in parallel using the circuits 352, 354, the decoder 350 may reduce a number of clock cycles associated with determining error locator information. Such a technique may be used to improve performance in certain applications, such as in connection with a nonbinary encoding technique that uses symbols to represent data, in which case determining the error parity 142 of
The operations 400 include an initialization operation, at 402. The initialization operation may include setting C(D), B(D), x, and b to one and setting L and T to zero. The initialization operation may include setting p to a value of the error parity 142 (e.g., to zero if the first data 134 has an even number of “1” values or to one if the first data 134 has an odd number of “1” values, as an illustrative example). In another example, the initialization operation may include setting p to a value of the even error parity 342 (e.g., by the first circuit 352) or setting p to a value of the odd error parity 343 (e.g., by the second circuit 354).
The operations 400 further include a set of summation operations, at 404.
The set of summation operations may include determining d, e_{1}, and e_{2}.
At 406, a determination is made whether d=0. If d=0, then the set of operations further includes increasing x by two (x=x+2), at 408, and increasing T (the iteration counter) by one (T=T+1), at 410. Otherwise, a determination is made whether L>T, at 412.
If L>T, the operations 400 further include adjusting C(D) based on C(D)=bC(D)+dD^{x}B(D), at 414. Otherwise, a determination is made whether the current degree L of the locator polynomial is equal to the iteration counter T (L=T) and whether the parity of L is equal to the parity of the errors (L(mod 2)=p), at 416.
If L=T and L(mod 2)=p, the operations 400 further include a first set of operations, at 418. The first set of operations may correspond to a “dualiteration” of a BM decoding process where L is increased by two. In this case, the operations 400 further include increasing T by two, at 422 (e.g., to indicate that operations of two iterations have been performed).
Otherwise, the operations 400 further include a second set of operations, at 420. The second set of operations may correspond to a “single iteration” of a BM decoding process where L is incremented by one. In this case, the operations 400 further include increasing T by two, at 410 (e.g., to indicate that operations of two iterations have been performed).
A determination may be made whether the iteration counter is greater than the error correction capability (T>t), at 424. If T≤t, the operations 400 may continue by performing the set of summation operations, at 404. Otherwise, if T>t, the operations 400 may end, at 426.
Referring to
The method 500 includes receiving first data at the decoder, at 502. For example, the decoder 150 may receive the first data 134.
The method 500 further includes generating second data at the decoder based on the first data, at 504. Generating the second data includes adjusting an error locator polynomial based on an error parity of the first data. To illustrate, the decoder 150 may generate the second data 136 by adjusting the length L of the error locator polynomial 152 based on the error parity 142.
Referring to
The method 600 includes generating an error locator polynomial based on first data using a first number of clock cycles of a clock signal, at 602. The first number is less than a number of errors of the first data. To illustrate, the first data 134 may include k errors, and the decoder 150 may generate the error locator polynomial 152 using j clock cycles of the clock signal 202, where j<k.
The method 600 further includes generating second data by adjusting the first data based on the error locator polynomial, at 604. As an illustrative example, the error corrector circuit 210 may identify the one or more error locations 212 based on the error locator polynomial 152, and the decoder 150 may adjust values of the first data 134 based on the one or more error locations 212 to generate the second data 136.
Referring to
The method 700 includes receiving data at a first circuit of the decoder, at 702, and receiving the data at a second circuit of the decoder, at 704. For example, the first circuit 352 and the second circuit 354 may receive the first data 134. In an illustrative example, the first circuit 352 and the second circuit 354 receive the first data 134 in parallel (e.g., during a common clock cycle).
The method 700 further includes performing a set of decoding operations at the first circuit based on the data by adjusting a first error locator polynomial based on an even error parity of the data, at 706. As an illustrative example, the first circuit 352 may adjust a length of the first error locator polynomial 358 based on the even error parity 342.
The method 700 further includes performing the set of decoding operations at the second circuit based on the data by adjusting a second error locator polynomial based on an odd error parity of the data, at 708. As an illustrative example, the second circuit 354 may adjust a length of the second error locator polynomial 359 based on the odd error parity 343.
In an illustrative example, the first circuit 352 performs the set of decoding operations in parallel with the set of decoding operations performed by the second circuit 354 (e.g., during a common set of clock cycles). The set of decoding operations may include one or more operations described with reference to the pseudocode of Example 1, one or more operations of the set of operations 400 of
The method 700 further includes selecting an output of the first circuit or the second circuit, at 710. For example, the third circuit 356 may select the first error locator polynomial 358 or the second error locator polynomial 359 as the output.
Overall latency at a decoder that uses an iterative error locator polynomial generation technique may be improved by determining a fast termination condition in parallel. For example, with reference to Table 1 and Example 1 described above in conjunction with the BerlekampMassey or the Improved BerlekampMassey techniques, each iteration of error locator polynomial generation evaluates d=Σ_{i=0}^{L}C_{i}S_{2T+1i}, and does not alter the current value of the error location polynomial C(D) if d=0. The condition d=0 may be typically satisfied once the error locator polynomial has converged to its final value. Further checking is performed to verify that the error locator polynomial has converged by checking that d continues to evaluate to 0 for each remaining iteration (e.g., until T>=t).
However, evaluation of d for the current value of the error location polynomial is based solely on the loop variable T, the polynomial length L, the polynomial coefficients c_{i}, and the syndromes S_{i}, all of which are known for the current value of the error location polynomial during each iteration. Therefore, computation of d for all remaining values of T may be performed in parallel, so that convergence or nonconvergence of the error locator polynomial at any particular iteration may be determined during a single decoding clock cycle. Convergence of the error locator polynomial may be detected prior to completion of the iterations described in Table 1 and Example 1, enabling fast termination of the error locator polynomial generation and reduced average decoding latency, as described further in the example of
Example 2 illustrates a modification of the pseudocode of Table 1 to include fast convergence detection, and Example 3 illustrates a modification of the pseudocode of Example 1 to include fast convergence detection.
In Examples 2 and 3, a convergence condition test has been added that calculates, during each iteration T, all d_{j }from j=T (the current iteration) to j=t−1 (the final scheduled iteration) to see if any changes to C(D) will occur in any remaining iteration. If all values of d_{j }are zero, convergence is detected.
Referring to
The syndrome generator 806 may be configured to process data read from the memory device 103 and to generate a set of syndromes corresponding to the received data. The set of syndromes may be provided to the error locator polynomial generator circuit 808. The error locator polynomial generator circuit 808 may be configured to perform an iterative process to generate an error locator polynomial. For example, the error locator polynomial generator circuit 808 may be configured to generate the error locator polynomial according to a BerlekampMassey (BM) technique, such as described with reference to Table 1. Alternatively, the error locator polynomial generator circuit 808 may perform a modified BM technique, such as described with reference to Example 1. Upon completion of generation of an error locator polynomial, the error locator polynomial generator circuit 808 may be configured to provide the error locator polynomial (or data corresponding to the error locator polynomial) to the root solver 810.
The root solver 810 may be configured to perform one or more search processes to determine roots of the error locator polynomial. For example, the root solver 810 may perform a Chien search to locate roots of the error locator polynomial. The decoder 802 may be configured to modify data read from the memory device 103 based on error location values indicated by the root solver 810 to generate errorcorrected data to be provided to the access device 170.
The convergence detector circuit 812 includes at least two parallel computation circuits including a first computation circuit 816 and a second computation circuit 818 in parallel with the first computation circuit 816. The multiple computation circuits may also include one or more other computation circuits, up to an N^{th }computation circuit 820, in parallel with the first computation circuit 816 and the second computation circuit 818.
Each of the N computation circuits 816820 may be configured to generate a respective convergence signal based on an error locator polynomial (ELP) 824 from the error locator polynomial generator circuit 808. For example, the first computation circuit 816 may be configured to generate a first convergence signal 830 based on the ELP 824. The first convergence signal 830 may correspond to a first iteration of the error locator polynomial generator circuit 808. Similarly, the second computation circuit 818 may be configured to generate, in parallel with generation of the first convergence signal 830 by the first computation circuit 816, a second convergence signal 832 based on the ELP 824 and corresponding to a second iteration of the error locator polynomial generator circuit 808. Because each of the computation circuits 816820 uses the same ELP 824 to generate its respective convergence signal, the ELP 824 may be referred to as a “mutual” error locator polynomial. Although each of the computation circuits 816820 uses the same error locator polynomial, each of the computation circuits 816820 uses a different set of syndromes than each of the other computation circuits 816820 to compute its respective convergence signal, as explained in further detail below.
The evaluation circuitry 822 may include a comparator, such as an adder or a logical OR gate. The evaluation circuitry 822 is coupled to the multiple computation circuits 816820 and is configured to generate an indicator 826 (e.g., a convergence indicator or a nonconvergence indicator) indicating whether a fast convergence condition has been detected. For example, the evaluation circuitry 822 may be configured to generate a nonconvergence indicator in response to receiving a convergence signal indicating nonconvergence (e.g., one or more of the signals 830834) from at least one of the multiple computation circuits 816820. The indicator 826 may be provided to the error locator polynomial generator circuit 808 to indicate whether convergence has been detected, such as via an interrupt signal that causes the error locator polynomial generator circuit 808 to halt processing and to provide the current version of the ELP 824 to the root solver 810.
Each of the comparison circuits 816820 may include a plurality of multipliers and an adder, such as a representative plurality of multipliers 840 and adder 842 of the first comparison circuit 816. Each multiplier of the plurality of multipliers 840 may be configured to multiply a syndrome value with a coefficient of the ELP 824, and the adder 842 may have inputs coupled to outputs of the plurality of multipliers 840. For example, the plurality of multipliers 840 and the adder 842 may be configured to perform the computation d=Σ_{i=0}^{L}c_{i}S_{2T+1i}, as in Table 1 or Example 1 (e.g., the plurality of multipliers 840 may include L+1 multipliers, each configured to multiply a respective coefficient c_{i }of the ELP 824 with a corresponding syndrome S_{2T+1i}). The first convergence signal 830 may have a logical “0” to indicate that d equals 0 (e.g., indicating possible convergence), or may have a logical “1” value to indicate that d does not equal 0 (e.g., indicating nonconvergence).
The convergence detector circuit 812 may configure each of the computation circuits 816820 to perform the computation d_{j}=Σ_{i=0}^{L}c_{i}S_{2j+1i }corresponding to a different iteration of the error locator polynomial generator circuit 808 (e.g., each of the computation circuits 816820 is assigned a value of j and computes a corresponding value of d_{j }as described in the pseudocode of Example 2 or Example 3. For example, during a first sequential iteration of the error locator polynomial generator circuit 808 (e.g., T=0 as in Table 1 or Example 1), the convergence detector circuit 812 may receive the ELP 824 for the first iteration and the first computation circuit 816 may perform the computation of d for the first value of j (i.e., j=T=0), the second computation circuit 818 may perform the computation of d for the second value of j (i.e., j=1), and the Nth computation circuit 820 may perform the computation for the (t−1)^{th }value of j (i.e., j=t−1), so that calculations of d for all the possible values of j of the error locator polynomial generator circuit 808 (i.e., for j=0 to j=t−1) are performed in parallel during a single clock cycle for the ELP 824 from the first iteration.
Although each of the computation circuits 816820 may use the same set of ELP coefficients {c_{0}, c_{1}, . . . , c_{L}}, each of the computation circuits 816820 may use a different set of the syndrome values. For example, when L=1, the first computation circuit 816 may use the set of syndromes {S_{0}, S_{1}} for j=0, the second computation circuit 818 may use a different set of syndromes {S_{2}, S_{3}} for j=1, and the Nth computation circuit 820 may also use a different set of syndromes {S_{2t2}, S_{2t1}} for j=(t−1). Thus, the convergence detector circuit 812 includes at least two computation circuits (e.g., computation circuit 816 and computation circuit 818) configured to generate at least two convergence signals (e.g., signals 830, 832) based on the same set of ELP coefficients e.g., ({c_{0}, C_{1}, . . . , C_{L}}) and based on at least two different sets of syndromes (e.g., {S_{0}, S_{1}} and {S_{2}, S_{3}}). Each of the different sets of syndromes corresponds to a different one of the convergence signals (e.g., when the first computation circuit 816 uses {S_{0}, S_{1}} during generation of the signal 830, the set of syndromes {S_{0}, S_{1}} corresponds to the signal 830; when the second computation circuit 818 uses set of syndromes {S_{2}, S_{3}} during generation of the signal 832, the set of syndromes {S_{2}, S_{3}} corresponds to the signal 832).
If all of the parallel computations of d equal 0, then the ELP 824 of the first iteration has a converged value and no further iterations of the error locator polynomial generator circuit 808 are needed. Otherwise, a second sequential iteration of the error locator polynomial generator circuit 808 may be performed (e.g., for T=1), a value of the ELP 824 for the second iteration may be received at the convergence detector circuit 812, and the first computation circuit 816 may perform the computation of d for the first value of j i.e. j=T=1, the second computation circuit 818 may perform the computation of d for the second value of j (i.e., j=2), and the (N−1)th computation circuit may perform the computation for the (t−1)^{th }value of j (i.e., j=t−1). Calculations of d for all remaining iterations of the error locator polynomial generator circuit 808 (i.e., for T=1 to T=t−1) are performed in parallel during the second clock cycle. Processing may continue for each sequential iteration of the error locator polynomial generator circuit 808 until convergence is detected (or until the process terminates at iteration T>=t without converging).
As described above, the convergence detector circuit 812 may include a sufficient number N of the computation circuits 816820 to enable a fully parallel convergence detection operation to complete in a single clock cycle. For example, the number N of computation circuits 816820 may substantially match “t”, the largest number of errors that are correctable by the ECC scheme. To illustrate, N may equal t or t1 in a particular implementation. However, in other implementations with relaxed latency criteria, a slower convergence detection (e.g., 2 or more clock cycles to detect convergence instead of a single clock cycle) may be attained with reduced hardware footprint and reduced cost by reducing the number N of computation circuits to be less than the largest correctable number of errors. For example, N may equal t/2, and convergence verification may be performed in two clock cycles. As another example, N may equal 2, and convergence verification may be performed in t/2 clock cycles. In implementations using multiclock cycle verification, it should be noted that although multiple clock cycles may be required to detect convergence, nonconvergence may be detected in a single clock cycle (e.g., in response to any of the computation circuits 816820 indicating a nonzero value of d).
In addition, as the number of iterations that have already been performed increases, the number of individual d computations that remain to verify convergence decreases. In an implementation where N equals t/2, 2clock cycle convergence verification may be performed for iterations of the first t/2 iterations (e.g., T<t/2), and 1clock cycle convergence verification may be performed for each of the last t/2 iterations (e.g., t/2<T<t).
Average decoding latency may also be improved using a decoding architecture that includes multiple parallel decoding paths, including one path that performs direct computation of error locations for a relatively small number of errors in parallel with another path that performs an iterative locator error polynomial generator for larger numbers of errors. An example of such an architecture that uses the modified BM technique to reduce iterations of the error polynomial generator is depicted in
The fast data path 904 may also be referred to as a direct solver circuit 904 that is coupled to a first input of the selector circuit 918 and configured to determine at least one error location. In the illustrated example, the fast data path 904 may include a direct computation unit 910 for computing the error locator polynomial (ELP) coefficients, and an ELP queue plus direct solver for ELP roots 912 (direct root solver). The direct computation unit 910 is configured to determine the coefficients of the ELP corresponding to the syndromes. The direct root solver 912 is configured to determine the roots of the ELP to thereby determine the error locations, which may be stored in an error locator queue.
The fast path 904 performs a “speculative” computation, meaning that the fast path computes TE different sets of ELP coefficients, and corresponding TE sets of speculative error locations. The fast path is set to converge (or commit) on a specific solution, only after the slow path 906 computes the degree L of the ELP. At this point, if L≤TE, the fast path will commit on the solution from the set of speculative solutions which corresponds to L. On the other hand, if L>TE the fast path 904 will not commit on a solution, and the decoding will continue until the slow path 906 converges to a solution. The slow path 906 includes an error locator polynomial generator circuit configured to adjust an error locator polynomial based on an error parity, such as an Improved BerlekampMassey algorithm (BMA) solver 914, for determining the coefficients of the ELP from the syndromes stored at the syndrome queue 902. The Improved BMA solver 914 may correspond to the modified BM decoder described with reference to
The syndrome queue 902 may be any suitable type of memory that may be used to store data such as the syndromes determined by the syndrome checkers, such as the syndrome generator circuit 204 in
In one implementation, the fast data path 904 may be operated as described below. A number of syndromes (S_{i}) for a received codeword are stored in the syndrome queue 902. Based on these syndromes, the direct computation unit 910 can perform a speculative direct computation of several candidate sets for the coefficients of the corresponding error location polynomial (ELP), which are provided to the direct root solver 912. The direct root solver 912 may have a queue or buffer for receiving the ELP coefficients determined by the direct computation unit 910, and is configured to determine the roots of the ELP, for each of the candidate sets of coefficients of the ELP.
The syndromes may be represented in terms of the ELP as follows:
Error location polynomial:
where Λ_{0}=1
In one implementation, referring to
If m=1 (first order ELP polynomial), the candidate set of coefficients of the ELP may be determined as follows:
Λ_{1}=S_{1 }
If m=2 (second order ELP polynomial), the candidate set of coefficients of the ELP may be determined as follows:
If m=3 (third order ELP polynomial), the candidate set of coefficients of the ELP may be determined as follows:
If m=4 (fourth order ELP polynomial), the candidate set of coefficients of the ELP may be determined as follows:
After the direct computation unit 910 computes all the candidate sets of coefficients of the ELP, they are stored at the direct root solver 912, which may have a queue or any suitable data storage for storing the coefficients. The direct root solver 912 is configured to solve for the roots of the ELP for each of the candidate set of coefficients. The direct root solver 912 may use any known methods to solve for the roots of the ELP. For small polynomial degrees, (e.g. 4) solving for the roots may be done by direct computations, i.e. by assigning specific values in predefined functions. Once the slow path 906 will compute the ELP degree, the fast path 904 may commit on the specific set of roots corresponding to the degree L computed by the BMA solver 914 (provided L≤4). The root(s) indicate the locations of the error bits in the received codeword. The error locations may be stored in the error location queue and may be provided to a code word queue that may correct the error bits in the received codeword based on the error locations. An error bit may be corrected by inverting or flipping the bit. An error location queue may be any suitable type of memory that may be used to store data. For example, an error location queue may be a randomaccess memory (RAM), a dynamic randomaccess memory (DRAM), a static randomaccess memory (SRAM), a synchronous dynamic randomaccess memory (SDRAM), a flash storage, an erasable programmable readonlymemory (EPROM), an electrically erasable programmable readonlymemory (EEPROM), or the like.
Referring to
Returning to
Although the fast path 904 generates error locations for a number of errors less than or equal to the threshold TE, the actual number of errors to be corrected is not determined until the error locator polynomial has been generated by the Improved BMA solver 914. The Improved BMA solver 914 may generate the error locator polynomial in fewer iterations (e.g., half as many iterations) as compared to the BM technique of Table 1, as described with reference to
Various modifications to the ECC circuitry 900 are possible. For example, in one implementation, the direct computation unit 910 and the Improved BMA solver 914 may be combined into a single solver device. In other implementations, some or all of the direct computation unit 910, the direct root solver 912, the Improved BMA solver 914, and the CRS root solver 916 may be included in the same device. In one implementation, the preselected error threshold (TE) may be four rather than six. In other implementations, the preselected error threshold (TE) can have other suitable values. The direct computation unit 910, the direct root solver 912, the Improved BMA solver 914, and CRS root solver 916 can each be implemented using any corresponding and suitable components as are known in the art.
In effect, the fast path 904 can provide quicker location of the errors in the codeword than the slow path 906. Each of the paths is configured to quickly and efficiently locate the errors based on the expected total number of errors in the syndrome, which may be later confirmed by convergence of the error locator polynomial. This twopath approach can provide quicker and more efficient error location than conventional single path approaches.
Decoding latency of the ECC circuitry 900 of
The convergence detector circuit 812 of
The convergence detector circuit 812 is configured to output a convergence signal to the control signal generator 922 upon detection of convergence of an error locator polynomial, enabling faster selection of an output of the fast path 1204 as compared to
Additional latency reduction may be achieved in implementations where the error locator polynomial generator 1204 implements an Improved BM technique as described with reference to
During an iteration prior to a final scheduled iteration of the error locator polynomial generation operation, multiple iterations of convergence criteria are concurrently tested to determine if a later iteration of the error locator polynomial generation operation is configured to change an error locator polynomial, at 1304. The convergence criteria may correspond to computations based on syndrome values and coefficients of the error locator polynomial, such as computations of d as described with reference to
For example, the multiple iterations of convergence criteria may correspond to all remaining iterations of the error locator polynomial generation operation and may be tested in parallel during a single clock cycle, such as in a fullyparallel implementation of the decoder 802 of
The error locator polynomial generation operation is terminated prior to the final scheduled iteration in response to determining that no later iteration of the error locator polynomial is configured to change the error locator polynomial, at 1306.
By terminating the error locator polynomial generation operation upon detection of convergence of the error locator polynomial (e.g., upon detecting that the error locator polynomial will not change in any future iteration), decoding latency may be reduced.
Referring to
The controller 1430 includes a decoder 1406 configured to detect fast convergence of an error locator polynomial generation. The decoder 1406 may correspond to the decoder 802 of
The controller 1430 (which may be a flash memory controller) may take the form of processing circuitry, a microprocessor or processor, and a computerreadable medium that stores computerreadable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. The controller 1430 may be configured with hardware and/or firmware to perform the various functions described below and shown in the flow diagrams. Also, some of the components shown as being internal to the controller 1430 can be stored external to the controller 1430, and other components can be used. Additionally, the phrase “operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.
As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller can have various functionality in addition to the specific functionality described herein. For example, the flash memory controller can format the flash memory, map out bad flash memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In operation, when a host device is to read data from or write data to the flash memory, the host device communicates with the flash memory controller. If the host device provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host device to a physical address in the flash memory. (Alternatively, the host device can provide the physical address.) The flash memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).
The one or more nonvolatile memory dies 1404 may include any suitable nonvolatile storage medium, including NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solidstate (e.g., flash) memory cells and can be onetime programmable, fewtime programmable, or manytime programmable. The memory cells can also be singlelevel cells (SLC), multiplelevel cells (MLC), triplelevel cells (TLC), or use other memory cell level technologies, now known or later developed. Also, the memory cells can be fabricated in a twodimensional or threedimensional fashion.
The interface between the controller 1430 and the one or more nonvolatile memory dies 1404 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the nonvolatile memory system 1402 may be a card based system, such as a secure digital (SD) or a micro secure digital (microSD) card. In an alternate embodiment, the nonvolatile memory system 1402 may be part of an embedded memory system.
Although, in the example illustrated in
Referring again to the controller 1430, a buffer manager/bus controller 1714 manages buffers in random access memory (RAM) 1716 and controls the internal bus arbitration of the controller 1430. A read only memory (ROM) 1718 stores system boot code. Although illustrated in
Front end component 1708 includes a host interface 1720 and a physical layer interface (PHY) 1722 that provide the electrical interface with the host device or next level storage controller. The choice of the type of host interface 1720 can depend on the type of memory being used. Examples of host interfaces 1720 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 1720 typically facilitates transfer for data, control signals, and timing signals.
Back end component 1710 includes an error correcting code (ECC) engine 1724 that encodes the data received from the host device, and decodes and error corrects the data read from the nonvolatile memory. A command sequencer 1726 generates command sequences, such as program and erase command sequences, to be transmitted to the one or more nonvolatile memory dies 1404. A RAID (Redundant Array of Independent Drives) component 1728 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the one or more nonvolatile memory dies 1404. In some cases, the RAID component 1728 may be a part of the ECC engine 1724. A memory interface 1730 provides the command sequences to nonvolatile memory die 1404 and receives status information from the one or more nonvolatile memory dies 1404. For example, the memory interface 1730 may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 1732 controls the overall operation of back end component 1710.
Additional components of the nonvolatile memory system 1402 illustrated in
In conjunction with the described embodiments, an apparatus includes means for generating an error locator polynomial (e.g., the decoder 150, the error locator polynomial generator circuit 208, the decoder 350, the error locator polynomial generator circuit 808, the error locator polynomial generator circuit 914, the error locator polynomial generator circuit 1214, or any combination thereof). The apparatus also include means for generating a first convergence signal based on the error locator polynomial and corresponding to a first set of syndromes (e.g., the first computation circuit 816). The apparatus also includes means for generating, concurrently with generation of the first convergence signal, a second convergence signal based on the error locator polynomial and corresponding to a second set of syndromes (e.g., the second computation circuit 818).
The apparatus may also include means for generating a nonconvergence indicator in response to at least one of the first convergence signal and the second convergence signal indicating nonconvergence and for generating a convergence indicator in response to all received convergence signals indicating convergence (e.g., the evaluation circuitry 822).
Although various components depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable such components to perform one or more operations described herein. For example, one or more of the syndrome generator 806, the error locator polynomial generator circuit 808, the root solver 810, or the convergence detector circuit 812 may represent physical components, such as hardware controllers, state machines, logic circuits, or other structures, to enable the decoder 802 to perform one or more operations described herein.
Alternatively or in addition, one or more of the syndrome generator 806, the error locator polynomial generator circuit 808, the root solver 810, or the convergence detector circuit 812 may be implemented using a microprocessor or microcontroller programmed to perform decoding operations. In a particular embodiment, one or more of the syndrome generator 806, the error locator polynomial generator circuit 808, the root solver 810, or the convergence detector circuit 812 include a processor executing instructions (e.g., firmware) that are stored at the memory 104. Alternatively, or in addition, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of the memory 104, such as at a readonly memory (ROM).
It should be appreciated that one or more operations described herein as being performed by the controller 130 and the controller 330 may be performed at the memory device 103. As an illustrative example, one or more decoding operations described with reference to the decoder 802 may be performed at the memory device 103.
The data storage devices 102, 302 may be coupled to, attached to, or embedded within one or more accessing devices, such as within a housing of the device 170. For example, the data storage devices 102, 302 may be embedded within the device 170 in accordance with a Joint Electron Devices Engineering Council (JEDEC) Solid State Technology Association Universal Flash Storage (UFS) configuration. To further illustrate, the data storage devices 102, 302 may be integrated within an electronic device (e.g., the device 170), such as a mobile telephone, a computer (e.g., a laptop, a tablet, or a notebook computer), a music player, a video player, a gaming device or console, an electronic book reader, a personal digital assistant (PDA), a portable navigation device, or other device that uses internal nonvolatile memory.
In one or more other implementations, the data storage devices 102, 302 may be implemented in a portable device configured to be selectively coupled to one or more external devices, such as a host device. For example, the data storage devices 102, 302 may be removable from the device 170 (i.e., “removably” coupled to the device 170). As an example, the data storage devices 102, 302 may be removably coupled to the device 170 in accordance with a removable universal serial bus (USB) configuration.
The device 170 may correspond to a mobile telephone, a computer (e.g., a laptop, a tablet, or a notebook computer), a music player, a video player, a gaming device or console, an electronic book reader, a personal digital assistant (PDA), a portable navigation device, another electronic device, or a combination thereof. The device 170 may communicate via a controller, which may enable the device 170 to communicate with the data storage devices 102, 302. The device 170 may operate in compliance with a JEDEC Solid State Technology Association industry specification, such as an embedded MultiMedia Card (eMMC) specification or a Universal Flash Storage (UFS) Host Controller Interface specification. The device 170 may operate in compliance with one or more other specifications, such as a Secure Digital (SD) Host Controller specification as an illustrative example. Alternatively, the device 170 may communicate with the data storage devices 102, 302 in accordance with another communication protocol. In some implementations, the data storage devices 102, 302 may be integrated within a networkaccessible data storage system, such as an enterprise data system, an NAS system, or a cloud data storage system, as illustrative examples.
In some implementations, one or both of the data storage devices 102, 302 may include a solid state drive (SSD). One or both of the data storage devices 102, 302 may function as an embedded storage drive (e.g., an embedded SSD drive of a mobile device), an enterprise storage drive (ESD), a cloud storage device, a networkattached storage (NAS) device, or a client storage device, as illustrative, nonlimiting examples. In some implementations, one or both of the data storage devices 102, 302 may be coupled to the device 170 via a network. For example, the network may include a data center storage system network, an enterprise storage system network, a storage area network, a cloud storage network, a local area network (LAN), a wide area network (WAN), the Internet, and/or another network.
To further illustrate, one or both of the data storage devices 102, 302 may be configured to be coupled to the device 170 as embedded memory, such as in connection with an embedded MultiMedia Card (eMMC®) (trademark of JEDEC Solid State Technology Association, Arlington, Va.) configuration, as an illustrative example. One or both of the data storage devices 102, 302 may correspond to an eMMC device. As another example, one or both of the data storage devices 102, 302 may correspond to a memory card, such as a Secure Digital (SD®) card, a microSD® card, a miniSD™ card (trademarks of SD3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). One or both of the data storage devices 102, 302 may operate in compliance with a JEDEC industry specification. For example, the data storage devices 102, 302 may operate in compliance with a JEDEC eMMC specification, a JEDEC Universal Flash Storage (UFS) specification, one or more other specifications, or a combination thereof.
The memory 104 may include a resistive random access memory (ReRAM), a flash memory (e.g., a NAND memory, a NOR memory, a singlelevel cell (SLC) flash memory, a multilevel cell (MLC) flash memory, a divided bitline NOR (DINOR) memory, an AND memory, a high capacitive coupling ratio (HiCR) device, an asymmetrical contactless transistor (ACT) device, or another flash memory), an erasable programmable readonly memory (EPROM), an electricallyerasable programmable readonly memory (EEPROM), a readonly memory (ROM), a onetime programmable memory (OTP), another type of memory, or a combination thereof. The memory 104 may include a semiconductor memory device.
Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, nonvolatile memory devices, such as resistive random access memory (“ReRAM”), magnetoresistive random access memory (“MRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of nonlimiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an antifuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of nonlimiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of nonlimiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure. In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an xz direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a nonlimiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in nonregular or nonorthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate). As a nonlimiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another nonlimiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an xz plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of nonlimiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xz) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a nonlimiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Alternatively, two dimensional arrays may be formed separately and then packaged together to form a nonmonolithic memory device having multiple layers of memory. For example, nonmonolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or nonmonolithic) may be formed on separate chips and then packaged together to form a stackedchip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As nonlimiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory readwrite operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
One of skill in the art will recognize that this disclosure is not limited to the two dimensional and three dimensional exemplary structures described but cover all relevant memory structures within the spirit and scope of the disclosure as described herein and as understood by one of skill in the art. The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Those of skill in the art will recognize that such modifications are within the scope of the present disclosure.
The abovedisclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, that fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.