Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence

• US 10,461,917 B2
• Filed: 03/13/2019
• Issued: 10/29/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Meninger, Scott E.
• Primary Examiner(s): Wong, Linda
• Application Number:
  US16/352,180
• Publication Number:
  US 20190215142A1
• Time in Patent Office: 230 Days
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

Claims

1. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to produce an on-chip reference clock signal; and

a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including an out-of-band parasitic pole, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor in combination with the out-of-band parasitic pole configured to suppress quantization noise introduced by modulating the frac-N PLL.

2. The circuit of claim 1, wherein the common PLL is configured to receive an off-chip reference clock signal generated external to the chip and wherein the on-chip reference clock signal is higher in frequency relative to the off-chip reference clock signal.

3. The circuit of claim 2, wherein the off-chip reference clock signal is configured to operate in a low frequency range of 100 MHz to 156 MHz and the on-chip reference clock signal is configured to operate in a higher frequency range of 400 MHz to 600 MHz.

4. The circuit of claim 1, wherein the circuit is configured to suppress modulation noise, generated by the frac-N PLL, by increasing frequency of the modulation noise to enable the frac-N PLL to filter the modulation noise.

5. The circuit of claim 1, wherein the frac-N PLL further includes a divider with a divide value, wherein the multiplying factor is configured to suppress an initial portion of the quantization noise, and wherein modulating the frac-N PLL includes modulating the divide value of the divider.

6. The circuit of claim 5, wherein the out-of-band parasitic pole is configured to suppress a remaining portion of the quantization noise, the remaining portion at higher offset frequencies relative to offset frequencies of the initial portion, the initial portion and the remaining portion suppressed below a noise level of noise generated from intrinsic phase detector and voltage controlled oscillator (VCO) noise sources on the chip.

7. The circuit of claim 1, wherein the frac-N PLL includes a divider and sigma-delta modulator, the sigma-delta modulator configured to modulate, randomly, a divide value of the divider.

8. The circuit of claim 7, wherein the frac-N PLL has an order that is lower relative to that of the sigma-delta modulator.

9. The circuit of claim 8, wherein the order of the frac-N PLL is two and that of the sigma-delta modulator is three.

10. The circuit of claim 1, wherein the common PLL is a first integer PLL, wherein the out-of-band parasitic pole is configured high enough to not affect closed-loop behavior of the frac-N PLL, and wherein the out-of-band parasitic pole in combination with configuration of the multiplying factor enable jitter and phase noise performance of the frac-N PLL to be comparable to that of a second integer PLL that employs a same integer divide value as the frac-N PLL.

11. The circuit of claim 1, wherein the frac-N PLL further includes a spread spectrum clock (SSC) pattern generator configured to modulate the frac-N PLL, directly, according to an SSC profile.

12. The circuit of claim 1, wherein:

the chip is a physical layer device (PHY);

the SerDes lane includes a transmitter configured to operate at a transmit data rate and a receiver configured to operate at a receive data rate;

the SerDes lane is configured to employ the transmit and receive data rates to communicate with a media access controller (MAC); and

the transmit and receive data rates are configured independent of data rates employed by other SerDes lanes of the PHY for communicating with other MACs.

13. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to produce an on-chip reference clock signal; and

a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including a divider with a divide value, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor configured to suppress a portion of quantization noise, the portion introduced by modulating the divide value of the divider of the frac-N PLL.

14. The circuit of claim 13, wherein the common PLL is configured to receive an off-chip reference clock signal generated external to the chip and wherein the on-chip reference clock signal is higher in frequency relative to the off-chip reference clock signal.

15. The circuit of claim 14, wherein the off-chip reference clock signal is configured to operate in a low frequency range of 100 MHz to 156 MHz and the on-chip reference clock signal is configured to operate in a higher frequency range of 400 MHz to 600 MHz.

16. The circuit of claim 13, wherein the circuit is configured to suppress modulation noise, generated by the frac-N PLL, by increasing frequency of the modulation noise to enable the frac-N PLL to filter the modulation noise.

17. The circuit of claim 13, wherein the frac-N PLL further includes a sigma-delta modulator, the sigma-delta modulator configured to modulate, randomly, the divide value of the divider.

18. The circuit of claim 13, wherein the portion is an initial portion and wherein the frac-N PLL further includes of an out-of-band parasitic pole configured to suppress a remaining portion of the quantization noise, the remaining portion at higher offset frequencies relative to offset frequencies of the initial portion, the initial portion and the remaining portion suppressed below a noise level of noise generated from intrinsic phase detector and voltage controlled oscillator (VCO) noise sources on the chip.

19. The circuit of claim 13, wherein the common PLL is a first integer PLL, wherein the frac-N PLL further includes an out-of-band parasitic pole configured high enough to not affect closed-loop behavior of the frac-N PLL, and wherein the out-of-band parasitic pole in combination with configuration of the multiplying factor enable jitter and phase noise performance of the frac-N PLL to be comparable to that of a second integer PLL that employs a same integer divide value as the frac-N PLL.

20. The circuit of claim 13, wherein the frac-N PLL further includes a sigma-delta modulator and wherein the frac-N PLL has an order that is lower relative to that of the sigma-delta modulator.

21. The circuit of claim 20, wherein the order of the frac-N PLL is two and that of the sigma-delta modulator is three.

22. The circuit of claim 13, wherein the frac-N PLL further includes a spread spectrum clock (SSC) pattern generator configured to modulate the frac-N PLL, directly, according to an SSC profile.

23. The circuit of claim 13, wherein:

the chip is a physical layer device (PHY);

the SerDes lane includes a transmitter configured to operate at a transmit data rate and a receiver configured to operate at a receive data rate;

the SerDes lane is configured to employ the transmit and receive data rates to communicate with a media access controller (MAC); and

the transmit and receive data rates are configured independent of data rates employed by other SerDes lanes of the PHY for communicating with other MACs.

24. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL), the common PLL configured to produce an on-chip reference clock signal; and

a serializer/deserializer (SerDes) lane including a fractional-N (frac-N) PLL, the frac-N PLL including a sigma-delta modulator, the on-chip reference clock signal distributed to the frac-N PLL, the frac-N PLL configured to have an order that is lower relative to that of the sigma-delta modulator of the frac-N PLL of the SerDes lane.

25. The circuit of claim 24, wherein the common PLL is configured to receive an off-chip reference clock signal generated external to the chip and wherein the on-chip reference clock signal is higher in frequency relative to the off-chip reference clock signal.

26. The circuit of claim 25, wherein the off-chip reference clock signal is configured to operate in a low frequency range of 100 MHz to 156 MHz and the on-chip reference clock signal is configured to operate in a higher frequency range of 400 MHz to 600 MHz.

27. The circuit of claim 24, wherein the order the frac-N PLL is two and that of the sigma-delta modulator is three.

28. The circuit of claim 24, wherein the circuit is configured to suppress modulation noise, generated by the frac-N PLL, by increasing frequency of the modulation noise to enable the frac-N PLL to filter the modulation noise.

29. The circuit of claim 24, wherein the frac-N PLL further includes a divider, the sigma-delta modulator configured to modulate, randomly, a divide value of the divider.

30. The circuit of claim 24, wherein the frac-N PLL further includes a divider with a multiplying factor and wherein the multiplying factor is configured to suppress an initial portion of quantization noise introduced by modulating the divide value of the divider.

31. The circuit of claim 30, wherein the frac-N PLL further includes an out-of-band parasitic pole configured to suppress a remaining portion of the quantization noise, the remaining portion at higher offset frequencies relative to offset frequencies of the initial portion, the initial portion and the remaining portion suppressed below a noise level of noise generated from intrinsic phase detector and voltage controlled oscillator (VCO) noise sources on the chip.

32. The circuit of claim 31, wherein the common PLL is a first integer PLL, wherein the out-of-band parasitic pole is configured high enough to not affect closed-loop behavior of the frac-N PLL, and wherein the out-of-band parasitic pole in combination with configuration of the multiplying factor enable jitter and phase noise performance of the frac-N PLL to be comparable to that of a second integer PLL that employs a same integer divide value as the frac-N PLL.

33. The circuit of claim 24, wherein the frac-N PLL further includes a spread spectrum clock (SSC) pattern generator configured to modulate the frac-N PLL, directly, according to an SSC profile.

34. The circuit of claim 24, wherein:

the chip is a physical layer device (PHY);

the SerDes lane includes a transmitter configured to operate at a transmit data rate and a receiver configured to operate at a receive data rate;

the SerDes lane is configured to employ the transmit and receive data rates to communicate with a media access controller (MAC); and

the transmit and receive data rates are configured independent of data rates employed by other SerDes lanes of the PHY for communicating with other MACs.