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Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence

  • US 10,461,917 B2
  • Filed: 03/13/2019
  • Issued: 10/29/2019
  • Est. Priority Date: 09/29/2017
  • Status: Active Grant
First Claim
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1. A circuit on a chip for serial data applications, the circuit comprising:

  • a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to produce an on-chip reference clock signal; and

    a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including an out-of-band parasitic pole, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor in combination with the out-of-band parasitic pole configured to suppress quantization noise introduced by modulating the frac-N PLL.

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