Synchronous transfer of streaming data in a distributed antenna system

• US 10,461,919 B2
• Filed: 07/16/2018
• Issued: 10/29/2019
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Outdoor Wireless Networks LLC (CommScope Holding Company, Inc.)
• Original Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Inventors: McAllister, Donald R., Ranson, Christopher Goodman, Phillips, Fred William
• Primary Examiner(s): Torres, Juan A
• Application Number:
  US16/036,541
• Publication Number:
  US 20180343106A1
• Time in Patent Office: 470 Days
• Field of Search: 375371
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04L 1/0625 Transmitter arrangements
• CPC Class Codes: H04L 1/0631 Receiver arrangements
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

A system includes: a unit configured to communicate a modulated signal via a signal interface; and at least one additional unit configured to receive the modulated signal from the unit. The at least one additional unit includes circuitry configured to remove jitter from a recovered clock signal to generate a jitter reduced clock signal that tracks long-term drift in the modulated signal, wherein the at least one additional unit is configured to generate the recovered clock signal from the modulated signal.

Claims

1. A system, comprising:

a unit circuitry configured to communicate a modulated signal via a signal interface; and

at least one additional unit circuitry configured to receive the modulated signal from the unit circuitry, the at least one additional unit circuitry including;

circuitry configured to remove jitter from a recovered clock signal to generate a jitter reduced clock signal that tracks long-term drift in the modulated signal, wherein the at least one additional unit circuitry is configured to generate the recovered clock signal from the modulated signal.

2. The system of claim 1, wherein the circuitry includes at least one of a phase-locked loop, a frequency-locked loop, or a narrowband filter.

3. The system of claim 1, further comprising scaling circuitry configured to scale a frequency of the recovered clock signal to generate an output signal at a predetermined target frequency.

4. The system of claim 1, wherein the signal interface is coupled to a communication medium, between the unit circuitry and the at least one additional unit circuitry, having at least one twisted pair cable.

5. The system of claim 1, the unit circuitry further including:

RF transceiver circuitry configured to communicate with a base transceiver station;

an auxiliary interface configured to communicate at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processor configured to multiplex data from the RF transceiver circuitry and the auxiliary interface for transmission to the at least one additional unit circuitry via the signal interface, the processor further configured to de-multiplex data received from the signal interface for transmission to the base transceiver station via the RF transceiver circuitry.

6. The system of claim 1, wherein the signal interface includes at least a one gigabit per second (Gbps) Ethernet interface.

7. The system of claim 6, wherein the Ethernet interface is synchronous.

8. A unit circuitry for use in a system comprising:

a signal interface configured to couple the unit circuitry to an additional unit circuitry of the system and to transceive a modulated signal with the additional unit circuitry; and

circuitry configured to generate a jitter reduced clock signal by removing jitter from a recovered clock signal while allowing the jitter reduced clock signal to track long-term drift in the modulated signal, wherein the unit circuitry is configured to generate a recovered clock signal from the modulated signal.

9. The unit circuitry of claim 8, wherein the circuitry includes at least one of a phase-locked loop, a frequency-locked loop, or a narrowband filter.

10. The unit circuitry of claim 8, further comprising scaling circuitry configured to scale a frequency of the recovered clock signal to generate an output signal at a predetermined target frequency.

11. The unit circuitry of claim 8, further comprising:

RF transceiver circuitry configured to communicate cellular and non-cellular data with a subscriber unit;

an auxiliary interface configured to communicate at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processing unit configured to de-multiplex data from the signal interface for transmission by the RF transceiver circuitry or the auxiliary interface, the processing unit is further configured to multiplex data from the RF transceiver circuitry and the auxiliary interface for transmission on the signal interface.

12. The unit circuitry of claim 8, wherein data communicated to the unit circuitry via the signal interface includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, Ethernet data, or WiFi data.

13. The unit circuitry of claim 8, wherein the signal interface includes at least a one gigabit per second (Gbps) Ethernet interface.

14. The unit circuitry of claim 11, wherein the processing unit is configured to adjust the rate of data being transmitted on the signal interface to match the capability of that signal interface.

15. The unit circuitry of claim 13, wherein the Ethernet interface is synchronous.

16. A method comprising:

receiving a modulated signal using a signal interface; and

generating a jitter reduced clock signal by removing jitter from a recovered clock signal while allowing the jitter reduced clock signal to track long-term drift in the modulated signal, wherein the recovered clock signal is generated from the modulated signal.

17. The method of claim 16, further comprising generating the jitter reduced clock signal by filtering the recovered clock signal using at least one of a phase-locked loop, a frequency-locked loop, or a narrowband filter.

18. The method of claim 16, further comprising scaling a frequency of the jitter reduced clock signal to produce at least one scaled clock signal.

19. The method of claim 16, wherein receiving the modulated signal comprises receiving the modulated signal using at least a one gigabit per second (Gbps) Ethernet interface.

20. The method of claim 16, wherein the communication medium is a communication cable having at least one twisted pair cable.