Sampler reference level, DC offset, and AFE gain adaptation for PAM-N receiver

• US 10,461,969 B2
• Filed: 04/19/2018
• Issued: 10/29/2019
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Wang, Nanyan
• Primary Examiner(s): Phu, Phuong
• Application Number:
  US15/957,737
• Publication Number:
  US 20180287831A1
• Time in Patent Office: 558 Days
• Field of Search: 375353, 375345, 375344, 375340
• CPC Class Codes: H04L 25/066 Multilevel decisions, not including self-organising maps
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 5/0048 Allocation of pilot signals, i.e. of signals known to the receiver

Abstract

In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

Claims

1. A method for adapting one or more reference voltages in a receiver, the method comprising:

receiving a first decoded data symbol at a first sample time, an edge symbol at an edge sample time following the first sample time, and a second decoded data symbol at a second sample time following the edge sample time;

determining, based on the first decoded data symbol, the second decoded data symbol, and the edge symbol, if a transition from the first decoded data symbol to the second data symbol meets transition criteria; and

responsive to determining that the transition meets the transition criteria, adjusting the one or more reference voltages based on the transition.

2. The method of claim 1, wherein determining that the transition meets the transition criteria comprises determining that an even number of symbols exists between the first decoded data symbol and the second decoded data symbol, and wherein adjusting the one or more reference voltages comprises:

adjusting a reference voltage in between the first decoded data symbol and the second decoded data symbol towards an amplitude of a pre-sliced edge sample corresponding to the edge symbol.

3. The method of claim 1, wherein determining that the transition meets the transition criteria comprises determining that an odd number of symbols exists between the first decoded data symbol and the second decoded data symbol, and wherein adjusting the one or more reference voltages comprises:

adjusting a reference voltage in between the first decoded data symbol and the second decoded data symbol towards a center symbol at a midpoint in between the first and second decoded data symbols.

4. The method of claim 1, wherein determining that the transition meets the transition criteria comprises determining that an even number of symbols exists between the first decoded data symbol and the second decoded data symbol and the edge symbol corresponds to a lesser of the first and second data symbols, and wherein

adjusting the one or more reference voltages comprises:

increasing a lowest reference voltage of the one or more reference voltages.

5. The method of claim 1, wherein determining that the transition meets the transition criteria comprises determining that an even number of symbols exists between the first decoded data symbol and the second decoded data symbol and the edge symbol corresponds to a greater of the first and second data symbols, and wherein adjusting the one or more reference voltages comprises:

decreasing a highest reference voltage of the one or more reference voltages.

6. The method of claim 1, wherein adjusting the one or more reference voltages comprises:

incrementing a cumulative error value if the edge symbol is equal to the symbol immediately below a first reference voltage;

decrementing the cumulative error value if the edge symbol value is equal to the symbol immediately above the first reference voltage; and

periodically updating a first error signal based on the cumulative error value, wherein an update period for updating the first error signal is longer than a sampling period for obtaining the decoded data symbols; and

adjusting the first reference voltage based on the first error signal.

7. The method of claim 1, further comprising performing a DC offset initialization of the one or more reference voltages prior to receiving the first and second decoded data symbols, wherein performing the DC offset initialization:

setting a center reference voltage of the one or more reference voltages at a predefined voltage level; and

adjusting a DC offset of incoming symbols until a number of incoming symbols above the center reference voltage is within a predefined range of a number of incoming symbols below the center reference voltage.

8. The method of claim 1, further comprising:

receiving, at an analog front end, an analog input signal;

converting, by the analog front end, the analog input signal to digital samples; and

adjusting a gain applied to the analog input signal in the analog front end based on adjustments to a maximum reference voltage and a minimum reference voltage of the one or more reference voltages.

9. A receiver circuit, comprising:

an error detection circuit to receive a first decoded data symbol at a first sample time, an edge symbol at an edge sample time following the first sample time, and a second decoded data symbol at a second sample time following the edge sample time, and to determine, based on the first decoded data symbol, the second decoded data symbol, and the edge symbol, if a transition from the first decoded data symbol to the second data symbol meets transition criteria; and

a reference level computation circuit to adjust the one or more reference voltages based on the transition responsive to determining that the transition meets the transition criteria.

10. The receiver circuit of claim 9, wherein the error detection circuit comprises logic to determine that an even number of symbols exists between the first decoded data symbol and the second decoded data symbol, and wherein the reference level computation circuit adjusts the one or more reference voltages by adjusting a reference voltage in between the first decoded data symbol and the second decoded data symbol towards an amplitude of a pre-sliced edge sample corresponding to the edge symbol.

11. The receiver circuit of claim 9, wherein the error detection circuit comprises logic to determine that the transition meets the transition criteria comprises determining that an odd number of symbols exists between the first decoded data symbol and the second decoded data symbol, and wherein the reference level computation circuit adjusts the one or more reference voltages by adjusting a reference voltage in between the first decoded data symbol and the second decoded data symbol towards a center symbol at a midpoint in between the first and second decoded data symbols.

12. The receiver circuit of claim 9, wherein the error detection circuit comprises logic to determine that an even number of symbols exists between the first decoded data symbol and the second decoded data symbol and the edge symbol corresponds to a lesser of the first and second data symbols, and wherein the reference level computation circuit adjusts the one or more reference voltages by increasing a lowest reference voltage of the one or more reference voltages.

13. The receiver circuit of claim 9, wherein the error detection circuit comprises logic to determine that an even number of symbols exists between the first decoded data symbol and the second decoded data symbol and the edge symbol corresponds to a greater of the first and second data symbols, and wherein the reference level computation circuit adjusts the one or more reference voltages by decreasing a highest reference voltage of the one or more reference voltages.

14. The receiver circuit of claim 9, wherein the reference level computation circuit is configured to increment a cumulative error value if the edge symbol is equal to the symbol immediately below a first reference voltage, decrement the cumulative error value if the edge symbol value is equal to the symbol immediately above the first reference voltage, periodically update a first error signal based on the cumulative error value, wherein an update period for updating the first error signal is longer than a sampling period for obtaining the decoded data symbols, and adjust the first reference voltage based on the first error signal.

15. The receiver circuit of claim 9, further comprising:

an analog front end to receive an analog input signal and convert the analog input signal to digital samples; and

a decoder to decode the digital samples to generate the first decoded data symbol and the second decoded data symbol.

16. The receiver circuit of claim 15, further comprising:

a DC offset circuit to offset the analog input signal by an offset voltage;

an adaptation circuit to set a center reference voltage of the one or more reference voltages at a predefined voltage level, and to adjust the offset voltage until a number of incoming symbols above the center reference voltage is within a predefined range of a number of incoming symbols below the center reference voltage.

17. The receiver circuit of claim 15, further comprising:

a DC offset circuit to offset the analog input signal by an offset voltage;

an adaptation circuit to adjust the offset based on adjustments to one or more center reference voltages.

18. The receiver circuit of claim 15, further comprising:

an amplifier to apply a gain to the analog input signal; and

an adaptation circuit to adjust the gain applied to the analog input signal in the analog front end based on adjustments to a maximum reference voltage and a minimum reference voltage of the one or more reference voltages.

19. A receiver circuit comprising:

an analog front end to receive an analog input signal;

an offset circuit to offset the analog input signal by an offset voltage to generate an offset analog input voltage;

an amplifier to apply a gain to the offset analog input signal to generate an amplified offset analog input signal;

an analog-to-digital converter to convert the amplified offset analog input signal to digital samples;

a decoder to decode the digital samples to generate output symbols at output sample times based on comparisons between the digital samples and a plurality of reference voltage and to generate edge symbols at edge sample times between the output sample times;

a reference level adaptation circuit to adjust the plurality of reference voltages based on the output symbols and the edge symbols;

an offset control circuit to control the offset voltage applied by the offset circuit based on the plurality of reference voltages; and

a gain control circuit to control the gain of the amplifier based on the plurality of reference voltages.

20. The receiver circuit of claim 19, the reference level adaptation circuit adjusts the plurality of reference voltages based on detected transitions between adjacent ones of the output symbols and an edge symbol in between the adjacent ones of the output symbols.