Glitch detector and test glitch generator

• US 10,466,275 B1
• Filed: 06/28/2018
• Issued: 11/05/2019
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Vundavalli, Sandeep, Saraswatula, Sree RKC, Wesselkamper, James D., Yachareni, Santosh, Zhou, Shidong, Kandala, Anil Kumar
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US16/022,403
• Time in Patent Office: 495 Days
• CPC Class Codes: G01R 11/24 Arrangements for avoiding or indicating fraudulent use
• CPC Class Codes: G01R 22/066 Arrangements for avoiding or indicating fraudulent use
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings

Abstract

Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

Claims

1. An integrated circuit (IC) tamper detection apparatus comprising:

a glitch detection circuit configured to receive a predetermined reference voltage signal (VREF) and a monitored supply voltage signal (MVSUPPLY), which is a function of a main supply voltage signal (VMAIN) configured to supply operating power to a target circuit, the glitch detection circuit comprising;

a first voltage divider configured to generate a plurality of voltage signals, each of the voltage signals representing a fraction of the MVSUPPLY voltage,

a first selection circuit configured to select one of the plurality of voltage signals in response to a glitch depth selection signal;

a comparator operably coupled to receive and compare the selected one of the plurality of voltage signals and the VREF to generate a depth detection signal (DEPTH_DET) in response to the MVSUPPLY transitioning from a nominal supply voltage range for the target circuit to a range between a minimum operating voltage and a power-on-reset voltage threshold for the target circuit; and

,

a glitch duration filter configured to receive the DEPTH_DET and a glitch width selection signal, the glitch duration filter configured to generate a glitch detection signal (DEPTH+WIDTH_DET) in response to the duration of the depth detection signal (DEPTH_DET) exceeding a selected glitch width responsive to the glitch width selection signal.

2. The IC tamper detection apparatus of claim 1, wherein the glitch detection circuit further comprises a latch configured to generate a latched glitch detection signal (GLITCH_DET_LATCHED) in response to the DEPTH+WIDTH_DET.

3. The IC tamper detection apparatus of claim 1, further comprising an input selection circuit configured to generate the MVSUPPLY, the input selection circuit comprising a test glitch generator configured to generate a test glitch signal, and a second selection circuit configured to generate the MVSUPPLY by selecting between the VMAIN and the test glitch signal.

4. The IC tamper detection apparatus of claim 3, wherein the test glitch generator is further configured to generate a test glitch signal in response to a signal indicating an amplitude and a duration of the test glitch signal.

5. The IC tamper detection apparatus of claim 4, wherein the test glitch generator comprises a second voltage divider configured to generate a plurality of test voltage signals, each of the test voltage signals representing a fraction of a test supply voltage.

6. The IC tamper detection apparatus of claim 5, wherein the test glitch generator further comprises a third selection circuit configured to select one of the plurality of test voltage signals.

7. The IC tamper detection apparatus of claim 1, further comprising at least two of the glitch detection circuits, wherein each of the at least two glitch detection circuits receives a unique combination of the glitch depth selection signal and the glitch width selection signal.

8. The IC tamper detection apparatus of claim 1, the glitch detection circuit further configured to receive its operating power from a supply voltage signal sourced with respect to the VMAIN.

9. The IC tamper detection apparatus of claim 1, further comprising a reference and supply circuit configured to generate and regulate the VREF.

10. The IC tamper detection apparatus of claim 9, wherein the reference and supply circuit further comprises a regulator to generate and supply power to the glitch detection circuit.

11. The IC tamper detection apparatus of claim 1, wherein the comparator is further operable to compare the selected one of the plurality of voltage signals and the VREF to generate a depth detection signal (DEPTH_DET) in response to the MVSUPPLY transitioning from a nominal supply voltage range for the target circuit to a range between a minimum operating voltage and a minimum specified power-on-reset voltage threshold for the target circuit.

12. A method of operating an integrated circuit (IC), the method comprising:

receiving, with a glitch detection circuit, a predetermined reference voltage signal (VREF) and a monitored supply voltage signal (MVSUPPLY), which is a function of a main supply voltage signal (VMAIN) configured to supply operating power to a target circuit, the glitch detection circuit operable to perform operations comprising;

generating, with a first voltage divider, a plurality of voltage signals, each of the voltage signals representing a fraction of the MVSUPPLY voltage,

selecting, with a first selection circuit, one of the plurality of voltage signals in response to a glitch depth selection signal;

receive and compare, with a comparator, the selected one of the plurality of voltage signals and the VREF to generate a depth detection signal (DEPTH_DET) in response to the MVSUPPLY transitioning from a nominal supply voltage range for the target circuit to a range between a minimum operating voltage and a power-on-reset voltage threshold for the target circuit; and

,

receiving, with a glitch duration filter, the DEPTH_DET and a glitch width selection signal, the glitch duration filter configured to generate a glitch detection signal (DEPTH+WIDTH_DET) in response to the duration of the depth detection signal (DEPTH_DET) exceeding a selected glitch width responsive to the glitch width selection signal.

13. The method of claim 12, the glitch detection circuit operable to perform operations comprising generating, with a latch, a latched glitch detection signal (GLITCH_DET_LATCHED) in response to the DEPTH+WIDTH_DET.

14. The method of claim 12, further comprising generating, with an input selection circuit, the MVSUPPLY, the input selection circuit comprising a test glitch generator configured to generate a test glitch signal, and a second selection circuit configured to generate the MVSUPPLY by selecting between the VMAIN and the test glitch signal.

15. The method of claim 14, further comprising generating, with the test glitch generator, a test glitch signal in response to a signal indicating an amplitude and a duration of the test glitch signal.

16. The method of claim 15, wherein the test glitch generator comprises a second voltage divider, and the method further comprises generating, with the second voltage divider, a plurality of test voltage signals, each of the test voltage signals representing a fraction of a test supply voltage.

17. The method of claim 16, wherein the test glitch generator further comprises a third selection circuit, and the method further comprises selecting, with the third selection circuit, one of the plurality of test voltage signals.

18. The method of claim 12, further comprising generating and regulating the VREF with a reference and supply circuit.

19. The method of claim 18, wherein the reference and supply circuit further comprises a regulator, and the method further comprises generating and supplying power, with the regulator, to the glitch detection circuit.

20. The method of claim 12, further comprising comparing, with the comparator, the selected one of the plurality of voltage signals and the VREF to generate a depth detection signal (DEPTH_DET) in response to the MVSUPPLY transitioning from a nominal supply voltage range for the target circuit to a range between a minimum operating voltage and a minimum specified power-on-reset voltage threshold for the target circuit.