Apparatus and method for accelerating operations in a processor which uses shared virtual memory
First Claim
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1. An apparatus comprising:
- front end hardware logic to couple to an accelerator, the front end hardware logic to receive and schedule tasks for execution on the accelerator, the front end hardware logic comprising;
a translation lookaside buffer (TLB) to store virtual-to-physical address mappings for the accelerator, wherein the accelerator comprises a memory manager to submit one or more TLB lookup requests to the TLB of the front end hardware logic, and wherein the front end hardware logic is to perform all TLB lookup operations required by the accelerator, including mapping virtual to physical address on behalf of the accelerator in response to the accelerator requiring access to a system memory; and
page walker circuitry to provide page walk services to the accelerator to determine virtual-to-physical address mappings.
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Abstract
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
37 Citations
14 Claims
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1. An apparatus comprising:
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front end hardware logic to couple to an accelerator, the front end hardware logic to receive and schedule tasks for execution on the accelerator, the front end hardware logic comprising; a translation lookaside buffer (TLB) to store virtual-to-physical address mappings for the accelerator, wherein the accelerator comprises a memory manager to submit one or more TLB lookup requests to the TLB of the front end hardware logic, and wherein the front end hardware logic is to perform all TLB lookup operations required by the accelerator, including mapping virtual to physical address on behalf of the accelerator in response to the accelerator requiring access to a system memory; and page walker circuitry to provide page walk services to the accelerator to determine virtual-to-physical address mappings. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11, 13)
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8. A non-transitory computer-readable medium having stored thereon hardware description language code to implement front end hardware logic for an accelerator, the front end hardware logic to:
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receive and schedule tasks for execution on the accelerator; and perform memory management operations, including; store virtual-to-physical address mappings for the accelerator in a translation lookaside buffer (TLB) of the front end hardware logic; receive from a memory manager of the accelerator one or more TLB look up requests; perform all TLB lookup operations required by the accelerator, including mapping virtual to physical address on behalf of the accelerator in response to the accelerator requiring access to a system memory; and provide page walk services to the accelerator to determine virtual-to-physical address mappings. - View Dependent Claims (12, 14)
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Specification