Command packets for the direct control of non-volatile memory channels within a solid state drive

• US 10,467,155 B2
• Filed: 10/26/2015
• Issued: 11/05/2019
• Est. Priority Date: 10/26/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: McVay, Jeffrey
• Primary Examiner(s): Park, Ilwoo
• Application Number:
  US14/923,269
• Publication Number:
  US 20170116139A1
• Time in Patent Office: 1,471 Days
• Field of Search: 710 5, 710 33, 710 74, 710105
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Apparatuses and methods for providing and interpreting command packets for the direct control of non-volatile memory channels within a solid state drive are disclosed herein. An example apparatus may include a plurality of flash memories configured into a plurality of channels and a controller coupled to the plurality of flash memories. The controller may be configured to receive a plurality of packets and interpret each packet of the plurality of packets based at least on a first protocol, and further configured to determine whether any packets of the plurality of packets are linked based on a link identifier included in a block of each packet, wherein a subset of packets of the plurality of packets are linked if they have the same link identifier, arrange the subset of packets based on an index included in the block of each packet of the subset of packets, wherein the subset of packets are arranged in order based on the respective indexes, determine a target flash memory and a target channel based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets, wherein each packet of the subset of packets identifies the same target flash memory and the same target channel, and provide data, address and control signals to the target flash memory based on interpreting the block of each packet of the plurality of packets based on a second protocol.

Claims

1. An apparatus, comprising:

a plurality of flash memories configured into a plurality of channels, wherein each of the plurality of channels includes one or more of the plurality of flash memories; and

a controller coupled to the plurality of flash memories and configured to operate using first and second protocols, receive a plurality of packets and use the first protocol to interpret each packet of the plurality of packets, wherein the controller is further configured to;

use the second protocol to determine whether any packets of the plurality of packets are linked based on a link identifier included in a block of each packet, wherein a subset of packets of the plurality of packets are linked if they have the same link identifier, and the link identifier is included in the block of each packet interpreted by using the second protocol;

arrange the subset of packets based on an index included in the block of each packet of the subset of packets, wherein the subset of packets are arranged in order based on the respective indexes;

determine a target flash memory and a target channel based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets, wherein each packet of the subset of packets identifies the same target flash memory and the same target channel; and

provide in each packet of the plurality of packets, data address and control signals to the target flash memory based on interpreting the block of each packet of the plurality of packets based on the second protocol different than the first protocol,

wherein the first protocol is a Non-Volatile Memory Express (NVMe) protocol, and the second protocol is an Open NAND Flash Interface (ONFI) protocol,

wherein the same controller is configured to use the NVMe protocol to interpret each packet of the plurality of packets, and use the ONFI protocol to interpret the block of each packet of the plurality of packets and provide, in each packet of the plurality of packets, the data, address and control signals to the target flash memory,

wherein the controller is further configured to use an index identifier to order a linked subset of packets of the subset of packets,

wherein the index identifier is included, in a higher byte than the link identifier, in a block of each of the linked subset of packets, the flash memo and channel identifiers are included, in higher bytes than both the index and link identifiers, in the block of each of the linked subset of packets, and the flash memory identifier is included in a higher byte than the channel identifier in the block, such that the block includes, in order, the flash memory identifier, the channel identifier, the index identifier, and the link identifier, and

wherein the ONFI protocol includes user-defined commands.

2. The apparatus of claim 1, wherein the controller comprises:

a frontend interface configured to interpret the plurality of packets based on the first protocol; and

a backend interface configured to interpret the block of each packet of the plurality of packets based on the second protocol.

3. The apparatus of claim 1, wherein the block of each packet of the plurality of packets further includes a plurality of control identifiers and a plurality of command identifiers, wherein each of the plurality of control identifier are associated with a subset of command identifiers of the plurality of command identifiers, wherein each of the control identifiers determines a type of command for each of the associated subset of command identifiers.

4. The apparatus of claim 3, wherein a set of bits of each of the plurality of control identifiers determine a command type of a respective one of the associated subset of command identifiers.

5. The apparatus of claim 3, wherein the command types may be one of a second protocol command, a second protocol address, a second protocol data, and a user-defined command.

6. An apparatus, comprising:

a controller configured to receive a plurality of command packets, interpret each of the plurality of received command packets based on a first protocol, and use a link identifier and an index identifier to order a linked subset of command packets of the plurality of command packets, the index identifier included, after the link identifier, in a block of each of the linked subset of command packets, the controller further configured to provide control signals and operands to a target flash memory of a plurality of flash memories over a target channel of a plurality of channels based on respective flash memory and channel identifiers included, after both the index and link identifiers, in the block of each of the linked subset of command packets, the flash memory identifier included after the channel identifier in the block, wherein at least the control signals and operands are determined based on interpreting at least a portion of each block of each of the linked subset of command packets based on a second protocol.

7. The apparatus of claim 6, wherein an operand type is determined by bits of an associated control byte included in each block of each of the linked subset of command packets.

8. The apparatus of claim 6, wherein each block of each command packet of the plurality of command packets includes entries directed at the second protocol, and wherein the entries directed at the second protocol provide low level flash memory control to the controller that the first protocol does not provide.

9. The apparatus of claim 6, wherein the operands are selected from one of an Open NAND Flash Interface (ONFI) command cycles, an ONFI address cycles, an ONFI data, and a non-ONFI command.

10. The apparatus of claim 6, wherein the controller is a solid state drive controller.

11. The apparatus of claim 10, wherein the solid state drive controller is coupled to a host via a Peripheral Component Interconnect Express bus, and wherein the first protocol is Non-Volatile Memory Express.