Cancelling adjacent track interference

• US 10,468,060 B1
• Filed: 09/27/2018
• Issued: 11/05/2019
• Est. Priority Date: 09/27/2018
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Wu, Zheng, Bellorado, Jason, Marrow, Marcus, Ashe, Vincent Brendan
• Primary Examiner(s): Hindi, Nabil Z
• Application Number:
  US16/144,659
• Time in Patent Office: 404 Days
• Field of Search: 360 25, 360 26, 360 39, 360 42, 360 50, 360 53, 360 65
• CPC Class Codes: G06F 17/17 Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method G06F17/18 takes precedence ; interpolation for numerical control G05B19/18
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/10231 wherein an asynchronous, free-running clock is used; Interpolation of sampled signals
• CPC Class Codes: G11B 20/10388 control of the read or write heads, e.g. tracking errors, defocus or tilt compensation
• CPC Class Codes: G11B 2005/0026 Pulse recording
• CPC Class Codes: G11B 5/00 Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor G11B11/00 and G11B13/00 take precedence
• CPC Class Codes: G11B 5/09 Digital recording

Abstract

An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.

Claims

1. An apparatus comprising:

a circuit configured to;

receive first underlying data corresponding to a first signal;

receive a second signal corresponding to second underlying data;

determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal;

determine estimated decisions corresponding to the second signal based on the second signal;

determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal;

generate a remaining signal based on the estimated signal and the second signal;

generate an error signal based on the interference component signal and the remaining signal; and

adapt one or more parameters of the first channel pulse response shape based on the error signal.

2. The apparatus of claim 1, the circuit further configured to:

cancel interference in the second signal using the interference component signal to generate a cleaned signal.

3. The apparatus of claim 2, further comprising the circuit further configured to:

generate a bit sequence corresponding to the second underlying data based on the cleaned signal.

4. The apparatus of claim 2, further comprising the circuit further configured to:

determine second estimated decisions corresponding to the second signal based on the cleaned signal;

determine a second estimated signal based on the second estimated decisions corresponding to the second signal and the second channel pulse response shape for the second signal; and

generate a second remaining signal based on the second estimated signal and the second signal.

5. The apparatus of claim 4, further comprising the circuit further configured to:

determine a second interference component signal based on the first underlying data corresponding to the first signal and the first channel pulse response shape for the first signal;

generate a second error signal based on the second interference component signal and the second remaining signal; and

adapt the parameters of the first channel pulse response shape based on the second error signal.

6. The apparatus of claim 5 further comprising the circuit configured to:

cancel interference in the second signal using the second interference component signal to generate a second cleaned signal; and

determine third estimated decisions corresponding to the second signal based on the second cleaned signal.

7. The apparatus of claim 1 further comprising the circuit configured to:

iteratively perform;

the determination of the second estimated decisions;

the determination of the second estimated signal the generation of the second remaining signal the determination of the second interference component signal the generation of the second error signal the adaptation of the parameters of the first channel pulse response shape based on the second error signal;

the cancellation interference in the second signal using the second interference component signal; and

the determination of the third estimated decisions;

discontinue iterations when the third estimated decisions pass an error correcting code check.

8. The apparatus of claim 2 further comprising the circuit configured to:

determine second estimated decisions corresponding to the second signal based on the cleaned signal;

determine a second estimated signal based on the second estimated decisions corresponding to the second signal and the second channel pulse response shape for the second signal;

generate a second remaining signal based on the second estimated signal and the second signal;

determine a second interference component signal based on the first underlying data corresponding to the first signal and the first channel pulse response shape for the first signal;

determine an error rate for the second estimated decisions;

selectively generate, when the error rate is below a threshold, a second error signal based on the second interference component signal and the second remaining signal; and

selectively generate, when the error rate is above the threshold, the second error signal based on the second interference component signal and the second signal.

9. The apparatus of claim 1 further comprising the circuit configured to:

interpolate the first underlying data to generate at least one interpolated signal using at least one respective finite impulse response filters; and

determine the interference component signal based on the first underlying data and the first channel pulse response shape at least in part by applying the first channel pulse response shape to the at least one interpolated signal.

10. The apparatus of claim 1, further comprising the second signal corresponding to a track of interest of a hard drive media with a first channel bit density and the first signal corresponding to an adjacent track to the track of interest with a second channel bit density.

11. A system comprising:

a first channel pulse response shape circuit configured to;

receive first underlying data corresponding to a first signal;

determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal; and

adapt one or more parameters of the first channel pulse response shape based on an error signal;

a detector circuit configured to;

receive a second signal corresponding to second underlying data;

determine estimated decisions corresponding to the second signal based on the second signal;

a second channel pulse response shape circuit configured to;

determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal;

a first adder configured to;

generate a remaining signal based on the estimated signal and the second signal; and

a second adder configured to;

generate an error signal based on the interference component signal and the remaining signal.

12. The system of claim 11 further comprising:

a third adder configured to;

cancel interference in the second signal using the interference component signal to generate a cleaned signal.

13. The system of claim 12 further comprising:

a second detector circuit configured to generate a bit sequence based on the cleaned signal, the second detector circuit being a primary channel detector of a channel of the system;

the first detector being a loop detector of the channel.

14. The system of claim 12 further comprising:

the detector circuit further configured to;

determine second estimated decisions corresponding to the second signal based on the cleaned signal;

the second channel pulse response shape circuit configured to;

determine a second estimated signal based on the second estimated decisions corresponding to the second signal and the second channel pulse response shape for the second signal; and

the first adder further configured to;

generate a second remaining signal based on the second estimated signal and the second signal.

15. The system of claim 14 further comprising the interpolator circuit further configured to:

the first channel pulse response shape circuit further configured to;

determine a second interference component signal based on the first underlying data corresponding to the first signal and the first channel pulse response shape for the first signal;

the second adder further configured to;

generate a second error signal based on the second interference component signal and the second remaining signal;

the first channel pulse response shape circuit further configured to;

adapt the parameters of the first channel pulse response shape based on the second error signal;

the third adder further configured to;

cancel interference in the second signal using the second interference component signal to generate a second cleaned signal; and

the detector circuit further configured to;

determine third estimated decisions corresponding to the second signal based on the second cleaned signal.

16. The system of claim 15 further comprising:

the first channel pulse response shape circuit, the detector circuit, the second channel pulse response shape circuit, the first adder, the second adder, and the third adder further configured to iteratively perform;

the determination of the second estimated decisions;

the determination of the second estimated signal the generation of the second remaining signal the determination of the second interference component signal the generation of the second error signal the adaptation of the parameters of the first channel pulse response shape based on the second error signal;

the cancellation interference in the second signal using the second interference component signal; and

the determination of the third estimated decisions;

discontinue iterations when the third estimated decisions pass an error correcting code check.

17. The system of claim 12 further comprising:

the detector circuit further configured to;

determine second estimated decisions corresponding to the second signal based on the cleaned signal;

determine an error rate for the second estimated decisions;

the second channel pulse response shape circuit configured to;

determine a second estimated signal based on the second estimated decisions corresponding to the second signal and the second channel pulse response shape for the second signal;

the first adder configured to;

generate a second remaining signal based on the second estimated signal and the second signal;

the first channel pulse response shape circuit further configured to;

determine a second interference component signal based on the first underlying data corresponding to the first signal and the first channel pulse response shape for the first signal; and

the second adder further configured to;

selectively generate, when the error rate is below a threshold, a second error signal based on the second interference component signal and the second remaining signal; and

selectively generate, when the error rate is above the threshold, the second error signal based on the second interference component signal and the second signal.

18. The system of claim 11 further comprising:

the second signal corresponding to a track of interest of a hard drive media with a first channel bit density and the first signal corresponding to an adjacent track to the track of interest with a second channel bit density a finite impulse response circuit configured to;

interpolate the first underlying data to generate at least one interpolated signal using at least one respective finite impulse response filters; and

the first channel pulse response shape circuit configured to;

determine the interference component signal based on the first underlying data and the first channel pulse response shape at least in part by applying the first channel pulse response shape to the at least one interpolated signal.

19. A method comprising:

receiving, by a first channel pulse response shape circuit, first underlying data corresponding to a first signal;

determining, by the first channel pulse response shape circuit, an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal;

receiving, by a detector circuit, a second signal corresponding to second underlying data;

determining, by the detector circuit, estimated decisions corresponding to the second signal based on the second signal;

determining, by a second channel pulse response shape circuit, an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal;

generating, by a first adder, a remaining signal based on the estimated signal and the second signal;

generating, by a second adder, an error signal based on the interference component signal and the remaining signal;

adapting, by the first channel pulse response shape circuit, one or more parameters of the first channel pulse response shape based on an error signal using least mean square (LMS) adaptation; and

cancelling, by a third adder, interference in the second signal using the interference component signal to generate a cleaned signal.

20. The method of claim 19 further comprising:

determining, by the detector circuit, second estimated decisions corresponding to the second signal based on the cleaned signal;

determining, by the detector circuit, whether the second estimated decisions pass an error correcting code check;

iteratively updating the second estimated decisions until the detector circuit determines the second estimated decisions passes the error correcting code check by;

determining, by the second channel pulse response shape circuit, a second estimated signal based on the second estimated decisions corresponding to the second signal and the second channel pulse response shape for the second signal;

generating, by the first adder, a second remaining signal based on the second estimated signal and the second signal;

determining, by the first channel pulse response shape circuit, a second interference component signal based on the first underlying data corresponding to the first signal and the first channel pulse response shape for the first signal;

generating, by the second adder further, a second error signal based on the second interference component signal and the second remaining signal;

adapting, by the first channel pulse response shape circuit, the parameters of the first channel pulse response shape based on the second error signal;

canceling, by the third adder, interference in the second signal using the second interference component signal to generate a second cleaned signal;

updating, by the detector circuit, the second estimated decisions corresponding to the second signal based on the second cleaned signal; and

determining, by the detector circuit, whether the updated second estimated decisions pass the error correcting code check.