Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication

• US 10,468,078 B2
• Filed: 03/24/2017
• Issued: 11/05/2019
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Fox, John, Holden, Brian, Shokrollahi, Amin, Singh, Anant, Surace, Giuseppe
• Primary Examiner(s): Abad, Farley
• Application Number:
  US15/469,441
• Publication Number:
  US 20170200482A1
• Time in Patent Office: 956 Days
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Claims

1. A method comprising:

obtaining memory transaction data at a link layer memory interface, and responsively forming a high-speed memory link packet having a set of multi-bit words;

storing each multi-bit word of the high-speed memory link packet as an entry in a first-in-first-out (FIFO) buffer;

obtaining, at an orthogonal signaling physical layer, a multi-bit word from the FIFO buffer, and consecutively encoding portions of the obtained multi-bit word into data codewords of an H4 balanced vector signaling code, wherein each data codeword comprises four symbols, one symbol having a value ±

1 and a remaining three symbols having a value ∓

⅓

, respectively;

transmitting a pre-designated packet start codeword of the balanced vector signaling code via high-speed data wires of a multi-wire bus; and

transmitting each data codeword via the high-speed data wires of the multi-wire bus.

2. The method of claim 1, further comprising formulating link layer packets at a first link layer controller for transmission over the orthogonal signaling physical layer to a second link layer controller.

3. The method of claim 1, further comprising transmitting chip-select signals via chips-select wires of the multi-wire bus.

4. The method of claim 1, further comprising transmitting a clock signal over a pair of high-speed clock wires of the multi-wire bus.

5. The method of claim 1, further comprising transmitting a pre-designated idle codeword prior to transmitting the pre-designated packet start codeword.

6. The method of claim 1, wherein the high-speed memory link packet is one of a memory write packet and a memory read request packet.

7. The method of claim 1, wherein the high-speed memory link packet is a memory read result packet.

8. The method of claim 1, wherein packet start and packet end timing is further obtained at the physical layer from the link layer memory interface.

9. An apparatus comprising:

a link layer memory interface configured to obtain memory transaction data, to responsively form a high-speed memory link packet having a set of multi-bit words, and to store each multi-bit word of the high-speed memory link packet as an entry in a first-in-first-out (FIFO) buffer; and

an orthogonal signaling physical layer configured to;

obtain a multi-bit word from the FIFO buffer, and to consecutively encode portions of the obtained multi-bit word into data codewords of an H4 balanced vector signaling code, wherein each data codeword comprises four symbols, one symbol having a value ±

1 and a remaining three symbols having a value ∓

⅓

, respectively;

transmit a pre-designated packet start codeword of the balanced vector signaling code via high-speed data wires of a multi-wire bus; and

transmit each data codeword via the high-speed data wires of the multi-wire bus.

10. The apparatus of claim 9, wherein the link layer is configured to formulate link layer packets at a first link layer controller for transmission over the orthogonal signaling physical layer to a second link layer controller.

11. The apparatus of claim 9, wherein the orthogonal signaling physical layer is further configured to transmit chip-select signals via chips-select wires of the multi-wire bus.

12. The apparatus of claim 9, wherein the orthogonal signaling physical layer is further configured to transmit a clock signal over a pair of high-speed clock wires of the multi-wire bus.

13. The apparatus of claim 9, wherein the orthogonal signaling physical layer is further configured to transmit a pre-designated idle codeword prior to transmitting the pre-designated packet start codeword.

14. The apparatus of claim 9, wherein the high-speed memory link packet is one of a memory write packet and a memory read request packet.

15. The apparatus of claim 9, wherein the high-speed memory link packet is a memory read result packet.

16. The apparatus of claim 9, wherein the physical layer is further configured to obtain packet start and packet end timing from the link layer memory interface.