Redundant voltage regulator for memory devices

• US 10,468,088 B2
• Filed: 12/15/2017
• Issued: 11/05/2019
• Est. Priority Date: 12/15/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Connolly, Brian J., Kim, Kyu-Hyoun, Maule, Warren E.
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/843,480
• Publication Number:
  US 20190189182A1
• Time in Patent Office: 690 Days
• Field of Search: 365226, 327540
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 29/702 by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

Claims

1. A system comprising:

at least one memory module including a plurality of dynamic random access memory devices mounted on the module, and a first voltage regulator mounted on the module, the first voltage regulator configured to supply at least one of a plurality of voltage levels to a plurality of voltage domains for supplying voltage to the plurality of memory devices, and

a system board including a second voltage regulator not mounted on the memory module configured to supply voltage to the first voltage regulator, and a third redundant voltage regulator, the third redundant voltage regulator configured to supply at least one of the plurality of voltage levels to the plurality of voltage domains on the memory module, wherein the at least one of the plurality of voltage levels supplied by the third redundant voltage regulator is the same voltage level as the at least one voltage level supplied by the first voltage regulator,

wherein the third voltage regulator is configured to be always actively on and supplying power to at least one of the voltage domains on the memory module along with the first voltage regulator.

2. The system of claim 1, wherein the third voltage regulator supplies the plurality of voltage levels to the voltage planes on the at least one memory module through a plurality of blade pins.

3. The system of claim 1, wherein the third voltage regulator is configured to continue to supply voltage to the plurality of voltage domains on the memory module in the event that the first voltage regulator fails.

4. The system of claim 1, wherein, the third voltage regulator is configured to supply the at least one of a plurality of voltage levels to the plurality of voltage domains in parallel to the at least one of the plurality of voltage levels supplied by the first voltage regulator.

5. The system of claim 1, wherein the memory module is configured to send a signal to the system board in response to an impending first voltage regulator failure.

6. The system of claim 5, wherein the signal sent to the system board upon impending failure of the first voltage regulator can be received from at least one of a RCD device mounted on the module, a special RFU pin on the module, or both.

7. The system of claim 1, wherein the system is configured so that a power-up sequence of the third voltage regulator occurs after a power-up sequence of the first voltage regulator has completed.

8. The system of claim 1, wherein the memory devices are configured to be accessed in reduced bandwidth frequency to secure the memory content of the memory devices in response to an event.

9. The system of claim 1, wherein the third voltage regulator improves the signal integrity of the memory devices by improving voltage tolerance of at least one voltage domain on the memory module.

10. The system of claim 1, wherein the third voltage regulator is configured to supply at least one of a plurality of voltage levels to a plurality of memory modules.

11. The system of claim 1, wherein the third voltage regulator is configured to supply 1.1 volts and 1.8 volts, and the second voltage regulator is configured to supply at least one voltage level including 12 volts.

12. A memory subsystem comprising:

at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator configured to supply a power supply signal from a system power supply and to output two or more power signals, each power signal providing a different, regulated voltage level, which regulated voltage levels are each configured to be routed to each of the plurality of memory chips; and

a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltage levels which are the same voltage levels as the voltage levels output by the voltage regulator on the memory module, and configured to supply the two or more power signals to the memory module,

wherein the at least one memory module is configured and adapted so that the plurality of voltage levels supplied by the redundant voltage regulator are parallel to the two or more power signals output by the memory voltage regulator.

13. The memory subsystem of claim 12, wherein the redundant voltage regulator is configured to output two or more power signals of different regulated voltage levels to a plurality of memory modules.

14. A method of powering memory devices comprising:

supplying at least two different, regulated voltage levels from a voltage regulator mounted on a memory module to two separate voltage domains; and

supplying at least two different, regulated voltage levels from a redundant voltage regulator to the memory module, the at least two different regulated voltage levels supplied by the redundant voltage regulator being the same voltage levels supplied by the voltage regulator mounted on the memory module,

wherein the redundant voltage regulator supplies power to the memory module through a larger blade pin to handle the increased current of supplying power at lower voltage.

15. The method of claim 14, wherein the redundant voltage regulator continues to supply the at least two different regulated voltage levels in the event the voltage regulator on the memory module fails.

16. The method of claim 14, further comprising generating a signal when the voltage regulator on the memory module fails.

17. The method of claim 16, wherein the memory module comprises a plurality of memory devices configured to store data, and the method further comprises moving the data from the plurality of memory devices to a safe location in the event the voltage regulator on the memory module fails.