Semiconductor memory having both volatile and non-volatile functionality and method of operating

• US 10,468,102 B2
• Filed: 08/09/2017
• Issued: 11/05/2019
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Reidlinger, R Lance
• Application Number:
  US15/673,059
• Publication Number:
  US 20170365340A1
• Time in Patent Office: 818 Days
• Field of Search: None
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Claims

1. A semiconductor memory cell comprising:

a fin structure extending from a substrate, said fin structure comprising a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and

a floating gate or trapping layer insulated from said floating body region and being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory;

wherein said charge flow into said floating body region upon restoration of power to said memory cell is non-algorithmically determined by said charge stored in said floating gate or trapping layer.

2. The semiconductor memory cell of claim 1, further comprising first and second regions in electrical contact with said floating body region, wherein each of said first and second regions has a conductivity type different from a conductivity type of said floating body region.

3. The semiconductor memory cell of claim 1, further comprising an isolation layer that isolates said floating body region from said substrate.

4. The semiconductor memory cell of claim 3, wherein said isolation layer comprises a buried oxide insulating layer.

5. The semiconductor memory cell of claim 3, wherein said isolation layer comprises a buried layer having a conductivity type different from a conductivity type of said floating body region.

6. The semiconductor memory cell of claim 1, wherein said floating gate or trapping layer is insulated from said floating body region by an insulating layer.

7. The semiconductor memory cell of claim 1, further comprising a control gate insulated from said floating gate or trapping layer by an insulating layer.

8. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows, wherein each said semiconductor memory cell comprises;

a fin structure extending from a substrate, said fin structure comprising a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and

a floating gate or trapping layer insulated from said floating body region and being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory;

wherein when said floating gate or trapping layer of a first memory cell of said plurality of semiconductor memory cells is in a first charge level and said floating gate or trapping layer of a second memory cell of said plurality of semiconductor memory cells is in a second charge level, upon restoration of power to said memory array, said floating body region of said first memory cell is charged to a first charge level as volatile memory and said floating body region of said second memory cell is charged to a second charge level as volatile memory; and

wherein said first and second charge levels as volatile memory are non-algorithmically determined by said first and second charge levels of said floating gate or trapping layer of said first and second memory cells, respectively.

9. The semiconductor memory array of claim 8, wherein each said semiconductor memory cell further comprises first and second regions in electrical contact with said floating body region, wherein each of said first and second regions has a conductivity type different from a conductivity type of said floating body region.

10. The semiconductor memory array of claim 8, wherein each said semiconductor memory cell further comprises an isolation layer that isolates said floating body region from said substrate.

11. The semiconductor memory array of claim 10, wherein said isolation layer comprises a buried oxide insulating layer.

12. The semiconductor memory array of claim 10, wherein said isolation layer comprises a buried layer having a conductivity type different from a conductivity type of said floating body region.

13. The semiconductor memory array of claim 8, wherein said floating gate or trapping layer is insulated from said floating body region by an insulating layer.

14. The semiconductor memory array of claim 8, wherein each said semiconductor memory cell further comprises a control gate insulated from said floating gate or trapping layer by an insulating layer.

15. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows, wherein each said semiconductor memory cell comprises;

a fin structure extending from a substrate, said fin structure comprising a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and

a floating gate or trapping layer insulated from said floating body region and being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory;

wherein upon restoration of power to said memory cell, said floating body region stores charge based on nonvolatile memory data stored in said floating gate or trapping layer; and

wherein said charge stored in said floating body upon restoration is non-algorithmically determined by said charge stored in said floating gate or trapping layer.

16. The semiconductor memory array of claim 15, wherein said semiconductor memory cell further comprises first and second regions in electrical contact with said floating body region, wherein each of said first and second regions has a conductivity type different from a conductivity type of said floating body region.

17. The semiconductor memory array of claim 15, wherein said semiconductor memory cell further comprises an isolation layer that isolates said floating body region from said substrate.

18. The semiconductor memory array of claim 17, wherein said isolation layer comprises a buried layer having a conductivity type different from a conductivity type of said floating body region.

19. The semiconductor memory array of claim 15, wherein said floating gate or trapping layer is insulated from said floating body region by an insulating layer.

20. The semiconductor memory array of claim 15, wherein said semiconductor memory cell further comprises a control gate insulated from said floating gate or trapping layer by an insulating layer.