Mechanisms for semiconductor device structure

• US 10,468,257 B2
• Filed: 08/18/2016
• Issued: 11/05/2019
• Est. Priority Date: 11/06/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Hsin-Ying, Wang, Mei-Yun, Wang, Hsien-Cheng, Yang, Fu-Kai, Liu, Shih-Wen, Hsu, Audrey Hsiao-Chiu
• Primary Examiner(s): Chen, Yu
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US15/240,680
• Publication Number:
  US 20160358779A1
• Time in Patent Office: 1,174 Days
• CPC Class Codes: H01L 21/0334 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.

Claims

1. A method for forming a semiconductor device structure, comprising:

forming a dummy gate structure over a substrate, wherein the dummy gate structure comprises a sidewall and a top surface;

forming a spacer on the sidewall of the dummy gate structure;

etching a top portion of the spacer to expose a top portion of the sidewall of the dummy gate structure and the top surface of the dummy gate structure;

forming a dielectric layer over the substrate to cover the top portion of the sidewall of the dummy gate structure after the top portion of the spacer is etched;

removing the dummy gate structure;

removing a portion of the dielectric layer to form a funnel shaped trench having a cone-shaped top portion and a tube-shaped bottom portion,

wherein the cone-shaped top portion has a sloping sidewall and a first end of the sloping sidewall is substantially level with a topmost of an interface between the spacer and the dielectric layer;

forming a gate structure in the tube-shaped bottom portion of the funnel shaped trench; and

filling a hard mask material in the cone-shaped top portion of the funnel shaped trench to form a funnel shaped hard mask structure.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein the cone-shaped top portion is formed by performing a plasma process, while the spacer is used to protect the bottom portion of the dielectric layer during the plasma process.

3. The method for forming a semiconductor device structure as claimed in claim 1, further comprising:

forming a contact though the dielectric layer, wherein the contact has an extending portion overlaying a portion of the funnel shaped hard mask structure.

4. The method for forming a semiconductor device structure as claimed in claim 1, wherein the dummy gate structure is completely removed before removing the portion of the dielectric layer to form a funnel shaped trench.

5. The method for forming a semiconductor device structure as claimed in claim 1, wherein the sloping sidewall extends from the first end to a second end and horizontally passed the outmost side of the spacer.

6. The method for forming a semiconductor device structure as claimed in claim 5, further comprising:

forming a source/drain region in the substrate,

wherein the second end of the sloping sidewall horizontally overlaps with the source/drain region.

7. The method for forming a semiconductor device structure as claimed in claim 1, wherein a portion of the funnel shaped hard mask structure extends horizontally passed an outmost side of the spacer.

8. A method for forming a semiconductor device structure, comprising:

forming a dummy gate structure over a substrate;

forming a spacer at a bottom portion of a sidewall of the dummy gate structure;

forming a dielectric layer over the substrate around the dummy gate structure and covered the spacer;

removing the dummy gate structure to form a tube-shaped trench;

forming a cone-shaped trench over the tube-shape trench;

forming a gate structure in a bottom portion of the tube-shaped trench; and

filling a hard mask material in the cone-shaped trench and a top portion of the tube-shaped trench to form a funnel shaped hard mask structure,

wherein a portion of the funnel shaped hard mask structure extends horizontally passed an outmost side of the spacer.

9. The method for forming a semiconductor device structure as claimed in claim 8, wherein the cone-shaped trench is formed by removing a portion of the dielectric layer located over the spacer.

10. The method for forming a semiconductor device structure as claimed in claim 9, wherein the portion of the dielectric layer is removed by performing a plasma process.

11. The method for forming a semiconductor device structure as claimed in claim 8, further comprising:

forming a spacer layer on a sidewall of the dummy gate structure;

etching back the spacer layer to form the spacer at the bottom portion of the sidewall of the dummy gate structure without covering a top portion of the sidewall of the dummy gate structure.

12. The method for forming a semiconductor device structure as claimed in claim 8, further comprising:

forming a contact though the dielectric layer, wherein the contact has an extending portion overlaying a portion of the funnel shaped hard mask structure.

13. A method for forming a semiconductor device structure, comprising:

forming a dummy gate structure over a substrate, wherein the dummy gate structure comprises a sidewall;

forming a spacer over a bottom portion of the sidewall of the dummy gate structure;

conformally forming a dielectric layer over and in direct contact with a side surface and a top surface of the spacer and on a top portion of the sidewall of the dummy gate structure;

removing a first portion of the dielectric layer to expose the dummy gate structure;

removing the dummy gate structure to form a tube-shaped trench;

after removing the dummy gate structure, removing a second portion of the dielectric layer from a top portion of the tube-shaped trench so that a cone-shaped trench is formed over the tube-shaped trench;

forming a gate structure in a bottom portion of the tube-shaped trench; and

forming a hard mask structure over the gate structure.

14. The method for forming a semiconductor device structure as claimed in claim 13, wherein the second portion of the dielectric layer is removed by performing a plasma process, while the spacer is used to protect a bottom portion of the dielectric layer during the plasma process.

15. The method for forming a semiconductor device structure as claimed in claim 13, wherein forming a hard mask structure over the gate structure further comprising:

filling a hard mask material in the cone-shaped trench and a top portion of the tube-shaped trench to form the hard mask structure.

16. The method for forming a semiconductor device structure as claimed in claim 15, further comprising:

forming a contact through the dielectric layer, wherein the contact has an extending portion overlaying a portion of the hard mask structure.

17. The method for forming a semiconductor device structure as claimed in claim 16, further comprising:

removing the extending portion of the contact overlaying the hard mask structure.

18. The method for forming a semiconductor device structure as claimed in claim 13, further comprising:

forming a spacer layer on a top portion and the bottom portion of the sidewall of the dummy gate structure;

forming a resist layer around the spacer layer;

removing a top portion of the resist layer to expose the spacer layer on the top portion of the sidewall of the dummy gate structure;

etching the top portion of the spacer layer exposed by the resist layer to form the spacer at the bottom portion of the sidewall of the dummy gate structure; and

removing the resist layer.

19. The method for forming a semiconductor device structure as claimed in claim 13, wherein the dummy gate structure comprises a top surface, and wherein the step of forming the spacer over the bottom portion of the sidewall of the dummy gate structure comprises:

forming a spacer layer on the sidewall of the dummy gate structure; and

etching a top portion of the spacer layer to expose a top portion of the sidewall of the dummy gate structure and the top surface of the dummy gate structure, thereby forming the spacer over the bottom portion of the sidewall of the dummy gate structure.

20. The method for forming a semiconductor device structure as claimed in claim 13, wherein a portion of the cone-shaped trench extends horizontally passed the outmost side of the spacer.