Apparatuses and methods for TSV resistance and short measurement in a stacked device

• US 10,468,313 B2
• Filed: 09/26/2017
• Issued: 11/05/2019
• Est. Priority Date: 09/26/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nishioka, Naohisa
• Primary Examiner(s): Anya, Igwe U
• Application Number:
  US15/715,504
• Publication Number:
  US 20190096776A1
• Time in Patent Office: 770 Days
• Field of Search: 257 48
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06544 : Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]

Abstract

Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.

Claims

1. An apparatus comprising:

a chip comprising;

a semiconductor substrate including a first surface and a second surface opposite to the first surface;

a first terminal formed above the first surface;

a second terminal formed above the second surface, wherein the second terminal is arranged to shift in a vertical direction without arranging above the first terminal in the vertical direction;

a buffer circuit coupled between the first and second terminals;

a first through-substrate via (TSV) penetrating the semiconductor substrate; and

a first switch coupled between the first terminal and the first TSV.

2. The apparatus of claim 1, wherein the chip comprises:

second, third, and fourth TSVs penetrating the semiconductor substrate;

a second switch coupled between the first terminal and the second TSV;

a third switch coupled between the second terminal and the third TSV; and

a fourth switch coupled between the second terminal and the fourth TSV.

3. The apparatus of claim 1, further comprising a control circuit configured to turn on the first switch in the at least one of the plurality of stacked chips in a test mode and turn off the first switch in each of the plurality of stacked chips in a normal mode.

4. The apparatus of claim 1, wherein the buffer circuit is configured to provide signals between the first and second terminals in response to input and output buffer control signals.

5. The apparatus of claim 1, wherein the buffer circuit comprises:

a read first in, first out (FIFO) buffer configured to provide signals from the first terminal to the second terminal; and

a write FIFO configured to provide signals from the second terminal to the first terminal.

6. An apparatus, comprising:

a chip comprising;

a semiconductor substrate including a first surface and a second surface opposite to the first surface;

a first terminal formed above the first surface;

a second terminal formed above the second surface, wherein the second terminal is arranged to shift in a vertical direction without arranging above the first terminal in the vertical direction;

a buffer circuit coupled between the first and second terminals;

a first through-substrate via (TSV) penetrating the semiconductor substrate; and

a first switch coupled between the first terminal and the first TSV, wherein the first switch is a p-type transistor.

7. An apparatus comprising:

first, second, third and fourth chips stacked in this order, each of the first, second, third and fourth chips including first, second, third and fourth terminals formed above a first surface thereof, a memory cell array, and a buffer circuit;

wherein each of the first, second and third chips includes fifth, sixth, seventh and eighth terminals formed above a second surface opposite to the first surface, the buffer circuit coupled in series between the first terminal and the eighth terminal, the second terminal coupled to the fifth terminal, the third terminal coupled to the sixth terminal and the fourth terminal coupled to the seventh terminal, and

wherein each of the first, second and third chips includes

first, second, third and fourth through-substrate vias (TSVs), each of the first to fourth TSVs penetrates a substrate; and

a control circuit configured to be able to connect the first terminal to at least one of the first and second TSVs and further configured to be able to connect the eighth terminal to at least one of the third and fourth TSVs.

8. The apparatus of claim 7, further comprising a force signal driver circuit configured to provide a constant current signal to the first terminal of each of the first, second, third, and fourth stacked chips.

9. The apparatus of claim 8, further comprising first, second, third, and fourth switches each configured to selectively couple a respective one of the fifth, sixth, seventh, and eighth terminals to the force signal driver circuit to provide a feedback signal.

10. The apparatus of claim 9, further comprising an output circuit configured to sense a total resistance through the second TSV of the first chip and the first TSV of the second chip.

11. The apparatus of claim 9, further comprising a control circuit configured to turn on the first switch in the at least one of the plurality of stacked chips in a test mode and turn off the first switch in each of the plurality of stacked chips in a normal mode.

12. The apparatus of claim 9, wherein each of the first, second, third and fourth chips further include a ninth terminal formed above the first surface and a tenth terminal formed above the second surface, wherein a fifth TSV couples the ninth terminal to the thirteenth terminal.

13. The apparatus of claim 12, wherein the ninth terminal is aligned with the tenth terminal.