Formation of fine pitch traces using ultra-thin PAA modified fully additive process

• US 10,468,342 B2
• Filed: 02/02/2018
• Issued: 11/05/2019
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Xiamen Compass Semiconductor Company Limited
• Original Assignee: Compass Technology Company, Limited
• Inventors: Pun, Kelvin Po Leung, Cheung, Chee Wah
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US15/887,346
• Publication Number:
  US 20190244882A1
• Time in Patent Office: 641 Days
• Field of Search: 257762, 174260
• CPC Class Codes: C23C 18/1641 Organic substrates, e.g. resin, plastic
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/1689 After-treatment
• CPC Class Codes: C23C 18/1692 Heat-treatment
• CPC Class Codes: C23C 18/2086 with use of organic or inorganic compounds other than metals, first
• CPC Class Codes: C23C 18/30 Activating or accelerating or sensitising with palladium or other noble metal
• CPC Class Codes: C23C 18/36 using hypophosphites
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: C25D 5/611 Smooth layers
• CPC Class Codes: C25D 5/617 Crystalline layers
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/26175 : Flow barriers
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48229 : the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81464 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/81466 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/81473 : Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85464 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/85466 : Titanium (Ti) as principal constituent
• CPC Class Codes: H01L 2224/85473 : Rhodium (Rh) as principal constituent
• CPC Class Codes: H01L 2224/86203 : Thermo-compression bonding
• CPC Class Codes: H01L 2224/8683 : Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

Claims

1. A chip on film comprising:

a flexible dielectric substrate having a first polyamic acid (PAA) anchoring layer on its top surface;

at least one first copper trace on a first Ni—

P seed layer on said first PAA layer and having a surface finishing layer on a top surface of said at least one first copper trace; and

at least one die mounted on said dielectric substrate to said at least one first copper trace.

2. The chip on film according to claim 1, further comprising:

a second PAA layer on a bottom surface of said dielectric substrate; and

at least one second copper trace on a second Ni—

P seed layer on said second PAA layer wherein said first and second copper traces are interconnected by a copper via through said dielectric substrate wherein said copper via further comprises a third PAA layer contacting said dielectric substrate and a third Ni—

P seed layer between said third PAA layer and said copper via.

3. The chip on film according to claim 1 wherein said flexible dielectric substrate comprises:

any kind of polyimide (PI), including Kapton PI or Upisel PI, or liquid crystal polymer (LCP).

4. The chip on film according to claim 1 wherein said first PAA layer has a thickness of less than 100 nm and preferably less than 10 nm.

5. The chip on film according to claim 1 wherein said first Ni—

P seed layer has a thickness of 0.1 μ

m+/−

10%, a surface roughness with Ra value below 100 nm, and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

6. The chip on film according to claim 1 wherein said at least one first copper trace has a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said at least one first copper trace is close to 1, wherein an elongation strength of said at least one first copper trace is over 15%, wherein a tensile strength of said at least one first copper trace is between about 290 and 340 N/mm², and wherein a hardness of said at least one first copper trace is 100 in vicker hardness with a purity of more than 99.9%.

7. The chip on film according to claim 1 wherein said surface finishing layer comprises electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG).

8. The chip on film according to claim 1 wherein a center to center distance between two adjacent said first copper traces is less than 8 μ

m.

9. The chip on film according to claim 1 wherein said second PAA layer has a thickness of less than 100 nm and preferably less than 10 nm.

10. The chip on film according to claim 2 wherein said second Ni—

P seed layer has a thickness of 0.1 μ

m+/−

10%, a surface roughness with Ra value below 100 nm, and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

11. The chip on film according to claim 2 wherein said at least one second copper trace has a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said at least one first copper trace is close to 1, wherein an elongation strength of said at least one first copper trace is over 15%, wherein a tensile strength of said at least one first copper trace is between about 290 and 340 N/mm², and wherein a hardness of said at least one first copper trace is 100 in vicker hardness with a purity of more than 99.9%.

12. The chip on film according to claim 2 wherein a center to center distance between two adjacent said second copper traces is less than 8 μ

m.

13. The chip on film according to claim 1 wherein a second peel strength of said chip on film after reliability tests of low temperature storage, high temperature storage, moisture sensitivity level-3, and thermal shock is the same or greater than a first peel strength of said chip on film before said reliability tests.

14. A chip on film comprising:

a flexible dielectric substrate having a first polyamic acid (PAA) anchoring layer on its top surface and a second PAA layer on its bottom surface;

at least one first copper trace on a first Ni—

P seed layer on said first PAA layer and at least one second copper trace on a second Ni—

P seed layer on said second PAA layer wherein said first and second copper traces are interconnected by a first copper via through said dielectric substrate wherein said first copper via further comprises a third PAA layer contacting said dielectric substrate and a third Ni—

P seed layer between said third PAA layer and said first copper via;

a first bonding film over said at least one first copper trace and a second bonding film over said at least one second copper trace;

an additional flexible dielectric substrate layer on said first and second bonding films and third and fourth at least one copper traces on third and fourth Ni—

P seed layers on third and fourth PAA anchoring layers on said third and fourth additional flexible dielectric substrate layers, respectively, wherein said at least one third and fourth copper traces are interconnected to underlying said first and second at least one copper traces, respectively, by second and third copper vias through said third and fourth additional PI or LCP layers and said first and second bonding layers, respectively, wherein said second and third copper vias further comprise a fourth PAA layer contacting said third and fourth additional flexible dielectric substrate layers and said first and second bonding layers, respectively, and a fourth Ni—

P seed layer between said fourth PAA layer and said second and third copper vias; and

at least one die mounted and bonded on a topmost of said at least one third or fourth copper trace.

15. The chip on film according to claim 14 wherein said flexible dielectric substrate and said additiona;

flexible dielectric substrate comprise;

any kind of polyimide (PI), including Kapton PI or Upisel PI, or liquid crystal polymer (LCP).

16. The chip on film according to claim 14 wherein said first, second, third, and fourth PAA layers have a thickness of less than 100 nm and preferably less than 10 nm.

17. The chip on film according to claim 14 wherein said first, second, third, and fourth Ni—

P seed layers have a thickness of 0.1 μ

m+/−

10% and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

18. The chip on film according to claim 14 wherein said at least one first, second, third, and fourth copper traces have a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said at least one first copper trace is close to 1, wherein an elongation strength of said at least one first copper trace is over 15%, wherein a tensile strength of said at least one first copper trace is between about 290 and 340 N/mm², and wherein a hardness of said at least one first copper trace is 100 in vicker hardness with a purity of more than 99.9%.

19. The chip on film according to claim 14 further comprising a surface finishing layer between said at least one third or fourth copper trace and said die wherein said surface finishing layer comprises electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG).

20. The chip on film according to claim 14 wherein a center to center distance between any two adjacent said first, second, third, or fourth copper traces is less than 8 μ

m.

21. The chip on film according to claim 14 further comprising any number of bonding layers, additional flexible dielectric substrate layers, and copper traces on top and bottom of said chip on film.

22. The chip on film according to claim 14 wherein a second peel strength of said chip on film after reliability tests of low temperature storage, high temperature storage, moisture sensitivity level-3, and thermal shock is the same or greater than a first peel strength of said chip on film before said reliability tests.