Semiconductor device

• US 10,468,511 B2
• Filed: 02/24/2017
• Issued: 11/05/2019
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ogura, Tsuneo, Matsudai, Tomoko
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US15/441,485
• Publication Number:
  US 20170271490A1
• Time in Patent Office: 984 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes a third electrode between a first semiconductor region and a second electrode, a fourth electrode between the first semiconductor region and the second electrode, a second semiconductor region between the first semiconductor region and the second electrode and between the third electrode and the fourth electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth electrode between the first semiconductor region and the second electrode to be electrically connected to the second electrode, and a fifth semiconductor region between the first electrode and the first semiconductor region. A first insulating film is provided between the third electrode and the first semiconductor region, the second semiconductor region, the third semiconductor region and the second electrode. A second insulating film is provided between the fourth semiconductor region and the first semiconductor region, the second semiconductor region, and the fourth semiconductor region.

Claims

1. A semiconductor device comprising:

a first electrode;

a second electrode;

a first semiconductor region of a first conductivity type that is provided between the first electrode and the second electrode;

a third electrode that is provided between the first semiconductor region and the second electrode;

a fourth electrode that is provided between the first semiconductor region and the second electrode and is aligned with the third electrode in a second direction intersecting a first direction toward the second electrode from the first electrode;

a fifth electrode that is provided between the first semiconductor region and the second electrode and is aligned with the fourth electrode in the second direction, the fifth electrode provided at an opposite side to the third electrode, and is in contact with the second electrode;

a second semiconductor region of a second conductivity type that is provided between the first semiconductor region and the second electrode and between the third electrode and the fourth electrode, and is electrically connected to the second electrode;

a third semiconductor region of the first conductivity type that is provided between the second semiconductor region and the second electrode and is electrically connected to the second electrode;

a fourth semiconductor region of the second conductivity type that is provided between the first semiconductor region and the second electrode to be electrically connected to the second electrode, and is aligned with the second semiconductor region via the fourth electrode in the second direction;

a first insulating film that is provided between (1) the third electrode and (2) the first semiconductor region, the second semiconductor region, the third semiconductor region, and the second electrode;

a second insulating film that is provided between (1) the fourth electrode and (2) the first semiconductor region, the second semiconductor region, and the fourth semiconductor region; and

a fifth semiconductor region of a second conductivity type that is provided between the first electrode and the first semiconductor region and is electrically connected to the first electrode, wherein an impurity concentration profile of the first semiconductor region in the first direction has a local maximum value between the third electrode and the fourth electrode and does not have the local maximum value between the fourth electrode and the fifth electrode.

2. The semiconductor device according to claim 1,

wherein a distance between (1) an interface between the fourth semiconductor region and the first semiconductor region and (2) the first electrode is shorter than a distance between (3) an interface between the second semiconductor region and the first semiconductor region and (2) the first electrode.

3. The semiconductor device according to claim 1, further comprising:

a third insulating film,

wherein

the third insulating film is provided between (1) the fifth electrode and (2) the first semiconductor region and the fourth semiconductor region, and

the fourth semiconductor region is provided between the fourth electrode and the fifth electrode.

4. The semiconductor device according to claim 3,

wherein the fourth electrode or the fifth electrode is electrically connected to the second electrode.

5. The semiconductor device according to claim 1,

wherein, in the second direction, a length of the fourth semiconductor region is longer than a length of the second semiconductor region.

6. The semiconductor device according to claim 1,

wherein the third semiconductor region is in contact with the first insulating film and does not contact with the second insulating film.

7. The semiconductor device according to claim 1,

wherein the second insulating film is provided between the fourth electrode and the third semiconductor region.

8. The semiconductor device according to claim 1,

wherein the third semiconductor region is provided as a plurality of regions disposed to be aligned in a third direction intersecting the first direction and the second direction.

9. The semiconductor device according to claim 1,

wherein the first semiconductor region has a region where an impurity concentration increases toward the first electrode.