Structure of trench metal-oxide-semiconductor field-effect transistor

• US 10,468,519 B2
• Filed: 04/24/2018
• Issued: 11/05/2019
• Est. Priority Date: 04/26/2017
• Status: Active Grant

• Current Assignee: National Tsing Hua University
• Original Assignee: National Tsing Hua University
• Inventors: Huang, Chih-Fang, Jiang, Jheng-Yi
• Primary Examiner(s): Patel, Reema
• Application Number:
  US15/961,043
• Publication Number:
  US 20180315848A1
• Time in Patent Office: 560 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.

Claims

1. A structure of a trench metal-oxide-semiconductor field-effect transistor (UMOSFET), the structure comprising:

a metal layer disposed on a top surface and a bottom surface of the structure to form a source and a drain, respectively, to function as electrodes of the structure connected to an external device;

an N-type semiconductor substrate disposed on the drain;

an N-drift region disposed on the N-type semiconductor substrate;

an N-current spread layer (N-CSL) disposed on the N-drift region;

a P-well disposed on the N-CSL;

an N-type semiconductor layer disposed on the P-well;

a first P-type semiconductor layer adjacent to the N-type semiconductor layer and disposed on the P-well;

a trench extending through the N-type semiconductor layer, the P-well and the N-CSL, wherein a bottom of the trench terminates at the N-drift region;

an insulating layer disposed in the trench;

a split gate disposed in the insulating layer of the trench and covered by the insulating layer;

a gate disposed in the insulating layer of the trench and above the split gate; and

a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias;

wherein the gate and the split gate are separated from each other by the insulating layer to form a predetermined gap; and

a depth position of a bottom of the gate is deeper than an interface between the P-well and the N-CSL;

a bottom surface of the split gate contacts an upper edge of the semiconductor protection layer.

2. The structure of the UMOSFET according to claim 1, wherein the semiconductor protection layer and the split gate are grounded to prevent a leakage current from being generated between the semiconductor protection layer and the split gate.

3. The structure of the UMOSFET according to claim 2, wherein the N-type semiconductor substrate, the N-CSL, the N-drift region and the N-type semiconductor layer are doped with an N-type semiconductor with concentrations satisfying:

the N-drift region<

the N-CSL.

4. The structure of the UMOSFET according to claim 3, wherein a capacitance between the gate and the split gate is smaller than a capacitance between the gate and the N-CSL;

and a distance between the gate and the P-well is smaller than the predetermined gap.

5. The structure of the UMOSFET according to claim 4, wherein the semiconductor protection layer is a second P-type semiconductor layer;

the structure is applicable to at least one of silicon carbide (SiC), gallium nitride (GaN) and silicon.