Vertical field effect transistor with improved reliability

• US 10,468,524 B2
• Filed: 03/24/2017
• Issued: 11/05/2019
• Est. Priority Date: 03/24/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Oldiges, Philip J., Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US15/468,300
• Publication Number:
  US 20180277674A1
• Time in Patent Office: 956 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.

Claims

1. A method for forming a semiconductor structure, the method comprising:

depositing a liner that conforms to a semiconductor fin;

removing a first portion of the liner including a first dielectric material from sidewalls of the semiconductor fin to create exposed portions of a source/drain region, while maintain a second portion of the liner;

forming a spacer layer on a second dielectric material and exposed portions of the source/drain region to form a step-shaped spacer; and

forming a gate material on the spacer layer to form a step-shaped gate.

2. The method of claim 1, wherein:

the semiconductor fin is formed on the source/drain region in a first direction; and

the second dielectric material is between the source/drain region and the spacer layer in the first direction.

3. The method of claim 2, wherein the source/drain region has a surface closer to the gate material than does a remaining portion of the liner including the first dielectric material in the first direction.

4. The method of claim 3, wherein:

forming the second dielectric material along the sidewalls of the remaining portion of the liner including the first dielectric material includes forming the second dielectric material on a surface of the source/drain region in a second direction; and

the second direction is orthogonal to the first direction.

5. The method of claim 1, further comprising:

removing a portion of the gate material, including exposing a portion of the spacer layer;

forming a dielectric layer on the portion of the spacer layer exposed by removing the portion of the gate material;

removing a portion of the dielectric layer on the portion of the spacer layer exposed by removing the portion of the gate material and a portion of the spacer layer exposed by removing the portion of the gate material; and

forming a contact to the source/drain region.

6. The method of claim 5, wherein the contact to the source/drain region contacts the remaining portion of the liner including the first dielectric material along sidewalls of the source/drain region.

7. The method of claim 5, further comprising forming a contact to the gate material.

8. The method of claim 1, further comprising:

forming the semiconductor fin on the source/drain region;

forming the liner including the first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region;

forming the second dielectric material along sidewalls of the liner including the first dielectric material.

9. The method of claim 1, wherein the spacer layer includes a dielectric material.

10. The method of claim 1, wherein the spacer layer includes a same material as the first dielectric material.

11. The method of claim 1, further comprising forming a second source/drain region on the semiconductor fin in the first direction.